EDSAC — Andrew Herbert

The EDSAC Replica Project charity has been merged with the TNMoC charity and the EDSAC Replica Project company has been wound up. The EDSAC Replica and associated equipment, documentation, spares etc. , are now formally part of TNMoC’s collection. This has been an agreed long-term intention of both parties, and now all the formalities have been completed.

My last report that Initial Orders loading into store was working turned out to be premature. We subsequently observed occasional miswrites, often of the form of orders being written in one location earlier than expected. This was eventually tracked down to the interaction between Main Control, Order Decoding and the Initial Orders subsystems. Initial Orders loading works by setting Main Control apparently executing orders from store, but with a special control signal set that converts the normal read of the next order to execute from store into a write of data coming from the Initial Orders uniselectors instead. It turned out when Initial Orders were being loaded, the signal to tell the store to write data into the appropriate tank was marginal. It also turned out that this signal triggered a read due to the analogue behaviour of read/write selection circuit. Attempts to suppress this were unsuccessful, but we then realised the read, while superfluous, is actually harmless. Accepting this, we have been able to simplify the read/write selection circuit and tune the inputs to the generation of the store write signal to give a decent pulse. Sorting this out should also improve matters for the EDSAC orders that write to store (F, I, T, U) although these are not yet sufficiently tested to be sure.

The paper tape reader circuits remain problematic for Martin Evans. The principle of operation is that after reading a character from the reader the circuit should set a RdrBusy signal that is long enough for the mechanical advance of the tape to the next character. This is around 100ms for the mechanical reader or 20ms for the photoelectric reader. As soon as RdrBusy is set the I (input) instruction completes, simultaneously setting a signal that inhibits incrementing the Sequence Control Tank (i.e. program counter). The effect is to make machine “spin” on the next I order until the Busy signal is reset. This is implemented using a monostable, but with the long delay required, the monostable is not ready in time to be retriggered once the RdrBusy signal clears. The current thought is to split the monostable into two monostables in series so that the first can be ready to be retriggered before the second has finished.

Nigel Bennée continues to commission the Arithmetic Unit. The delay line team (Peter Linington and Peter Haworth) at Nigel’s invitation replaced the Digital Tank Emulator for the Multiplier register with a short nickel delay line, which has worked well. The delay line has been seen to reliably hold data from one week to the next. However, in replacing the delay line it was found the buffered clock distribution in the Arithmetic Unit was not producing a sufficiently strong clock to drive the nickel delay line and a clock had to be borrowed from elsewhere in the machine. Nigel has now revised the Arithmetic Unit clock distribution and the clock pulse levels are sufficient to drive nickel delay lines in the unit’s various registers.

Simon Porter has connected another two “EDLA” monitoring probes to EDSAC. (Both in fact are “PEDLAs”, using a Raspberry Pi, but essentially functionally equivalent to the earlier EDLAs). Together this provides Brian Knight, who is developing the monitoring system, with sufficient information to be able to monitor correct execution of orders, and give helpful reports when errors occur. Simon also continues to maintain our circuit schematics library and the Initial Orders system.

When we have both Initial Orders loading and the paper tape reader functional, we should be able to load programs as was done on the original via the “START” button, rather than through the current backdoor of a microprocessor “Signal Sequence Injector” that writes directly to the store.

Remaining work is therefore: 1) complete tape reader, 2) add printer, 3) commission all arithmetic functions and 4) complete monitoring system.

Elliott 803, 903 & 920M — Terry Froggatt

The new mains distribution board has now been installed at TNMoC, but neither the 803 nor the 903 are yet using the new earth-leakage circuit breakers, which are being tripped by both machines. As I reported in the previous issue of Resurrection, we know how to fix this problem, at least on the 903.

Meanwhile, Peter Williamson reports that the 903 has some other problems:

• The expansion memory PSU has a fault: the +6V supply is not regulating correctly. Peter has brought some replacement power transistors but has not had time to fit one. At the moment the 903 is running in 8K mode.
• The punch has recently stopped working. The motor will power up but none of the solenoids will activate. It could be the +28V supply, even though it is correctly driving the paper tape reader clutch, or it could be a logic signal which affects all of the solenoids. The problem also affects the control panel run-out button, but manually depressing the tape feed solenoid does cause run-out to work.
• Finally the Q-register bit-10 problem reappeared recently, but it went after re-seating the board.

Peter Onion tells me that his team has restored a spare 803 console that has been in the upstairs boiler room at TNMoC for many years. He is thinking about making it into an exhibit that can be taken to shows, by connecting it up to an emulation and maybe some real peripherals (like a reader or punch).

As promised in the previous issue of Resurrection, regarding my description of the 920M at www.tjfroggatt.plus.com/MCM7.HTM: I’ve now posted a four-page UPDATE. PDF with corrections to several files, most significantly to LOGICSUB.PDF & EXPLANAT.PDF.

None of the 920Ms that we have has a control panel, so restarting a program involves turning the power off and on again (which is far from ideal), rather than using the RESET then JUMP buttons on the control panel. Experimentally, I linked a switch and a 100Ω resistor between the (normally low) RESET pin 33 and +5V on pin 74 of a 920M control panel socket SKTG. Closing the switch did indeed reset the 920M, and opening it caused a jump (to 8181 or 8177 as usual), without needing the JUMP pin. Problem solved.

This highlights a difference between the 920Ms examined, and the 920B or 903 which have a reset latch in the CPU, set by RESET and cleared by JUMP. I’ve found no latch in the MCM7 variant of the 920M, but there are two gates which could have been wired as a latch in the earlier MCM2 & MCM5 variants. This accords with my memory of using the earlier 920M variants in the 1970s at Elliotts with a 920B-style control panel. Our MCM7 variants probably need 920C-style control panels.

Data Recovery — Delwyn Holroyd

In my last report I described the work done to create a functional MFM disc emulator for the ICL System 25 at TNMoC. My colleague Johan has been writing a simple boot loader and demonstration programs with the help of a software simulator. The data file used by the simulator is then converted to a disc image file suitable for loading onto the hardware emulator.

After making a small modification to one of the programs, one sector could not be read with the System 25 disc controller returning a diagnostic code of ‘Sector Not Found’. This was unexpected to say the least as my analysis routines confirmed that all the sectors were present and all CRC checks passed. Furthermore we found that changing just a single byte in the demonstration program cured the problem!

After a lot of head scratching I realised that the physical sector before the apparently missing sector on the track had a CRC which contained both sync (00h) and address mark (A5h) bytes, which got me suspicious. Changing any byte in this sector changed the CRC to something completely different and the following sector could be read.

A close study of images we captured from real System 25 discs showed that the gaps between sectors were filled not with sync (00h) bytes as specified in the technical description on which I based my implementation, but a sequence of junk having no special meaning to the hardware. Replacing the sync bytes in the gap with junk resolved the problem. It appears that the presence of these special bytes in the CRC, followed by the sequence of sync bytes in the gap was confusing the sector search algorithm of the disc controller.

Johan has now written some test programs to fully exercise the disc emulator. I’m pleased to report that no further issues have been discovered.

Harwell Dekatron — Delwyn Holroyd

If any of the sending Dekatrons fail to circulate during an arithmetic operation, the machine should stop with all the transfer unit trigger tubes lit except for the one corresponding to the digit which failed to circulate. For some time there has been an intermittent fault in this process whereby sometimes the lit trigger tubes extinguish one by one over a period of seconds to minutes after the stop. This has now been tracked down to a dirty relay contact in the circulation check signal path. The result was a wandering voltage which in turn caused the trigger tube anode HT supply voltage to droop, causing the symptoms observed.

Aside from this, the machine has continued to run well, although we have received reports from demonstrators that occasionally, arithmetic operations are coming up with the wrong results! This is under investigation.

ICL 2966 — Delwyn Holroyd

Following the gallery re-organisation earlier in the year, we have now completed a project to replace all the informational signage. The new signs are printed on foam board with a consistent template across the whole gallery. There are more than 20 boards for the 2966 and its related exhibits, which include a number of 1900 objects as well as the peripherals and terminals. New introductory boards have been hung on the DCU cabinets.

Two recent donations have been put on display in the 2966 area – a picture of a large 1906A installation, and a store motherboard from one of the Series 39 DM1 prototypes.

The 2966 itself continues to run well, and we are in the process of training another operator. There were a few days during the summer when the machine had to be turned off earlier in the day than planned as the temperature in the OCP had reached our limit of 42C. The limit is somewhat arbitrary, but was set slightly above the 35-39C which is routinely reached on a normal day (bearing in mind there is no air chiller, just large extractor fans).

ICL 1900 — David Wilcox, Bill Gallagher, Delwyn Holroyd

David has made considerable progress with the 7903 comms processor – 7181 VDU emulation. Still working on some of the more intricate parts of the screen handling but the basic functionality is there and I have used it running against my George 3 system.

Bill continues to scan manuals from the late Brian Spoor’s collection.

Software — David Holdsworth

I have the website working on Windows 10, ubuntu 18 and Raspberry Pi. The software is identical on all three environments, except that the emulator code written in C needs to be compiled for each platform.

I received an offer of help from Anthony Smith (newly retired) and he is doing a review of the site in the hope of identifying aspects that are not self-explanatory. Also, he is trying to arrange a visit to the Vintage ICL Computer Museum.

Ferranti Argus 700 — Peter Harry

Our Argus 700 continues to operate reliably and provide demonstrations at the RAF Air Defence Museum, Neatishead.

The Argus 700 is at the bottom of the nearest rack racks. I/0 rack nearest, the Argus 700 is centre of the furthest rack. The CHARGE ‘box’ and contains the four sets of PCBs of the display system

A task that has become routine before running the Argus is to reseat and/or clean the DIN connectors in the CHARGE display system’s PCBs. The reason for this is that the CHARGE chassis is at the bottom of the I/O rack and adjacent to the cabin door. Prior to recovering the cabin, it had been abandoned in the open for many years and for long periods the cabin door was left open resulting in the CHARGE chassis and its four sets of display PCBs being rained on! A refurbishment of the CHARGE chassis is currently beyond our capabilities, so we continue to reseat and clean the PCB connectors before each operating session.

Away from Neatishead, work continues with a focus on maintaining the stock of spare Argus 700 PCBs. Several PCBs that make up the Argus processor contain crystal oscillators which are stuck to the PCB with a piece of thin rubberised tape, possibly required by the original flow soldering. Unfortunately, a chemical reaction has resulted in the corrosion of the case on all crystals, a problem identified some time ago. All spare PCBs are now having their crystals changed and the remains of the sticky rubber tape removed. An additional problem on a couple of PCBs is detached leads on some metal oxide resistors. There is some evidence that the PCBs in question may not have been stored in the best environmental conditions.

Corroded Crystal	Detached Resistor Leads

Around ten years ago we started to use the SCS2SD SCSI-2 disc emulator due to problems with the supply and reliability of original rotating media (Seagate 31200N, 1.05Gb). Unfortunately, our Argus 700 is locked into this model of SCSI-2 disk due to a configuration sector and its content on the disc being set by an EPROM on the SCSI controller. The SCSI2SD emulator is no longer available and is replaced by ZULUSCSI, a new product using a different technology for emulation. Both use full size SD cards, but they are not interchangeable! Configuring and testing the ZULUSCSI for use in the Argus 700 is now complete after some ‘fiddling’ resulting from Argus discs using 256 Byte sectors. How much easier would support be if Ferranti had opted for 512 Byte sectors?

ICT 1301 — Rod Brown

Since the 1301 system hardware was stored at TNMoC, the 1301 project has focused on the software for the system and its recovery.

Having delivered several introductions to historic computing to local groups and U3A members this year, there seems to be a growing interest is the software, partially driven by the good work at TNMoC on the “Virtual Flossie” project and also the principles of emulation using modern computing techniques.

I do not know what the outcome of the current interest will be, but at least seven people are now discussing an emulation on modern equipment.

SSEM — Bob Geatrell

Following a period where Baby was rather unpredictable for 10-15 minutes after switch on, it has settled down and for the last few weeks the daily reports has begun with “Baby ran well today”.

The museum is looking forward to the imminent re-opening of the main power hall, which has been closed for building renovation works for several years. The planned redevelopment of the display area around Baby is moving back into focus and we are starting detailed discussions about a full modernisation of Baby’s power supplies. Baby has been running successfully for many months with three commercial off the shelf 50v PSU modules replacing two of the increasingly fragile 75v Post Office PSUs. These have given good service since the rebuild but are difficult to maintain. We intend to replace the remaining PSUs with the modern units and move the entire stack just out of view of the visitors. In future, we expect that any power failures will be managed by the simple replacement of a (cost effective) 50v module allowing volunteers to focus on the skills required to understand and maintain Baby itself.

It is also gratifying that another young volunteer has recently joined the team. Although she works during the week, if does mean that Baby can be staffed regularly at weekends when, of course, the museum has rather more visitors.

A cache of papers including Turing’s PhD dissertation given by Alan Turing to a friend were found during a house clearance recently. They narrowly avoided being shredded until somebody had the idea that it might be worth asking whether they were potentially valuable. As it turned out they were. Handled by Rare Book Auctions they realised £465,400 including £208,000 for a copy of the famous On Computable Numbers paper. See www.ccsoc.org/bbc0.htm and www.ccsoc.org/rar0.htm for more details. Thanks to CCS member, Steve Ripley for the lead.

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Sharp-eyed readers will have noticed more changes on the inside of the back cover of Resurrection. all our committee members have been allocated an email address within the ccsoc. org internet domain. They are not real email accounts but redirections and are intended to try to shield committee members from unwanted junk mail and worse. Previous addresses in the computerconservationsociety. org domain will continue to work.

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It is with much sadness that we have heard of the passing of Dame Stephanie (“Steve”) Shirley, a significant figure in the UK IT industry. Founding Freelance Programmers Ltd – an organisation of largely female, home-based programmers, Dame Stephanie did more than anybody to sweep away the male domination of the industry in the ’60s and ’70s. We can do no better than refer readers to Georgina Ferry’s excellent Guardian obituary at www.ccsoc.org/fer0.htm.

We were contacted by the TV producers of Great British Rail Journeys hosted by Michael Portillo. They were asking whether we could put them in touch with the IBM Museum at Hursley Park. Well of course we could! Within five minutes! Keep an eye on the Radio Times. Other listings magazines are available or so I’m told.

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Dr Peter Kemp of King’s college London is researching the early history of computers in UK schools. He contacted BCS in the person of Martin Cooper (he of IT Now) who passed the query onto us. Circulating the note to the usual suspects brought forth a veritable tidal wave of material contained in no less than 28 emails (at the time of writing).

But Dr Kemp is particularly interested in an IBM project to develop a suitable computer for schools (www.ccsoc.org/ibm3.htm). Apparently, the computer was never put into production and, beyond what is on this web page. Our friends at Hursley have drawn a blank so far.

So, if anybody knows any more about it, we’d be glad to hear of it. Contact . if you can help

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Similarly, Dr Richard O’Keefe is looking into the history of the Pop-2 programming language, originally developed by Robin Popplestone at the University of Edinburgh.

www.ccsoc.org/pop2.htm lists most of what he has. He also has a manual for Pop-2 on the Elliott 4100 and the IMP source code of EMAS Pop-2, but no documentation, and the source code for its library is missing.

He is looking for reference material for other implementations, especially Robert Rae’s WPOP, and for software written in Pop-2. Any information on how implementations worked would also be of interest.

Contact . if you can help.

I am pleased to report another active and energetic year for the Society.

There have been eight hybrid London Meetings held at the BCS London headquarters and online as well as the traditional December film show organised by Dan Hayton. Topics ranged from Leonardo Torres Quevedo, pioneer of computing, automatics and artificial intelligence, an amazing Spanish polymath working in the late 19^th and early 20^th centuries, to Lore Harp and her company Vector Graphics, Silicon Valley’s forgotten female microcomputer pioneers. Thanks are due to Roger Johnson for his continuing organisation of a most interesting series of talks.

North West branch has held one hybrid meeting this year. Kevin Hughes spoke on ‘50 Years of the ICL New Range’, organised by Bob Geatrell and Alan Pickwick.

Members continue to work on a substantial number of projects relating to historic computers, including the Manchester Baby, the Harwell Dekatron, aka The Witch computer, ICL 1900 and 2966, a replica of the EDSAC and many more. There is also a software conservation project, and IBM Hursley Museum has a large collection of IBM artefacts, many of them under restoration.

Communication with and between members. The CCS was originally set up not only to investigate and record the history of computers and software, but also to facilitate communication between members who have particular interests within the broad scope of the Society’s remit, such as individual brands or ranges of computer. Until the advent of GDPR, that is what we did. However, since the BCS implemented GPDR in a very strict way, we have been able to communicate to all members but not to individual members and members could not communicate with other members through the CCS.

We have been pressing BCS management for several years to enable us to fulfil our mission. In the past year we have at last made significant progress and are in the process of building our own database of members’ email addresses, using Mailchimp, and to store in it any information members choose to share, such as machines in which they are interested or have expertise, CCS projects they are engaged in, their physical address (so that they can link up with others in their area), etc. What they share will be entirely up to the individual member. Initially the database will hold email addresses of non-BCS members of the CCS. Members of the CCS who are also members of the BCS will have the option to have the CCS database hold their information too. As soon as the BCS releases the lists to us, we will populate the database and then we can begin to use the database for regular emails and developing more interaction between members who share interests. We expect it to be available shortly. Huge thanks to Bill Barksfield who has worked with BCS Management, educated them in Mailchimp, convinced them that it is safe and reliable and conforms to GDPR, and is setting the system up.

There were three most interesting editions of Resurrection. Many thanks to Dik Leatherdale for encouraging, assembling and editing the articles for each edition, and for managing the Society’s website.

Dan Hayton, Dik Leatherdale and Martin Campbell-Kelly continued the collection and preservation of the Society’s digital and video archives, including photographs, and thus recording the Society’s history.

This summer the annual visit to a computer museum took a party of 30 to the National Museum of Scotland Collections Centre in Granton, Edinburgh. The collection included parts of a Ferranti Atlas as well as a section of a Ferranti Mark 1, including a Williams Tube storage device. Other specially built machines for Scottish educational institutes were on display along with machines from Elliott, ICL, Burroughs and other manufacturers. We are grateful to Tacye Phillipson and her colleagues for guiding us round the centre.

Rachel Boon has been appointed the Science Museum’s representative to the Committee.

I would like to record my gratitude to the members of the Committee including the leaders of the various projects referred to above, which report to the Committee, for all their support and hard work. I could not have led the Society without their generous support.

This year’s CCS “overseas” trip was to Edinburgh, organised as usual by Dan Hayton. “Hardly overseas” I hear you say, and well within the catchment area of the British Computer Society, albeit outside the range of a Sassenach bus pass. But the admirably-frequent Lothian buses do now accept a credit-card tap, with a daily cap for three or more trips.

Some two dozen of us got together for dinner at Howies, Victoria Street, in the Old Town, on the Monday evening, where I found myself sitting opposite someone who I’d last seen in York in 1978. The three-course meal was good, with most of us opting for the haggis starter.

Thirty of us met on the afternoon, of Tuesday 2^nd September, at the Museum of Scotland’s collection centre in Granton, where we were split into two groups. One group was shown around the “large computer” collection by the senior curator Dr Tacye Phillipson, whilst the other group was shown around the “large objects” collection by principal curators Drs Rebekah Higgitt & Meredith Greiling. After an hour we swapped round.

Tacye showed us a rather interesting collection of vintage computers (and some drum stores) including a Ferranti Mark 1*, a Ferranti Mercury, parts of a Leo III from Phoenix Assurance, and parts of the Chilton Atlas 1, “the most powerful computer in the world” (in its time). Our worthy editor Dik had once used this very Atlas at Chilton. There was also a 1/16 scale of model of an Atlas.

Several computer cabinets had information about their contents Sellotaped to the inside of their doors, and Tacye was keen to explain that the crumbling Sellotape was part of the artefact and should not be replaced until it gave way.

I last visited this collection in 2014, when I did a detailed survey of their two Elliott 903s, and I was glad to see them again. There are also several Elliott 803 cabinets, upside down because they have gone weak in the legs, and a couple of analogue machines (one of which had probably been used for calculating chicken food mixtures), and a machine for making punched cards.

In the “large objects” collection, Rebekah showed us an 1884 bullion balance named “The Lord High Chancellor” from the Bank of England, made by Napier & Son (but not known relatives of the logarithmic Napier), an early bubble-chamber particle detector, and a brace of lighthouse heads.

My thanks to Dan, Tacye, Rebekah & Meredith, for making this expedition possible.

The ACE family

Figure 1 – the evolution of the ACE architecture and its realisation in working machines

ACE was designed to be a large machine, with fast memory and a hardware system that would be as simple as possible. Mercury delay lines were chosen for the main memory. The outline design was completed by the end of 1945, physical realisation was achieved by the National Physical Laboratory (NPL), who designed pilot ACE and full ACE, English Electric, who delivered DEUCE and the Post Office, who built MOSAIC for the Radar Research and Development Establishment (RRDE).

Both Pilot ACE and DEUCE were based on version V of Turing’s architecture MOSAIC and Full ACE were built on later versions: VII and VIII respectively. The last two used four-addressing, allowing them to execute an instruction simultaneously addressing two source operands, a destination address and the next instruction. Table 1 gives a top-level comparison between the ACE iterations described.

Table 1 – High level summary of ACE lineage hardware differences

Pilot Ace

Pilot ACE had: 11 long delay lines, numbered DL1..... DL11, two double delay lines, DS12 and DS14, and 5 one-word short delay lines: TS15, TS16, TS20, TS26, TS27. Each short line held one 32-bit word and the time taken for a single bit to traverse it was called a minor cycle. Long lines held 32 words and the time taken for a single bit to traverse a long line was known as a major cycle (i.e. 32 minor cycles). A specific long line address was represented by adding the relevant minor cycle m to the delay line number n, as DLn_m. An instruction within ACE occupied a word and took the form shown in figure 2.

Figure 2: The format of the Pilot ACE word

The addressing capability was defined by the size of the source and destination fields (five bits each) and the next instruction field (3 bits) – hence the term 3 address. There was no explicit function or operation code and only one source address was specified. Further, arithmetic and logical operations exclusively used short or double delay lines. The operation to be performed was inferred from the source and destination addresses used. For example, specifying a source of 15 and a destination of 16 moved the contents of TS15 to TS16, however if the destination of 16 is changed to 17, the contents of TS15 would be added to those of TS16 and stored there. Table 2 maps the source, destination and next instruction numbers, indicating where specific instructions are implicated.

The GO bit, when set, ensured an instruction was executed immediately, when it was not set (called a stopper instruction), the instruction waited on an external event.

Table 2 Source and Destination interpretation for Pilot ACE

The wait, timing and characteristic fields determined the sequence of operation. Each instruction took a minimum of two minor cycles to execute, the first cycle, known as the setup beat, assimilated the instruction in the control part of the machine and the number of remaining execution cycles (the obey cycle) was determined by the setting of the wait number W and timing number T. An instruction occupying position m in a long line and with a wait number W and timing number T began the transfer in minor cycle (m + W+ 2) and the next instruction was accessed during minor cycle (m + T + 2) from the selected next instruction source. If characteristic was 0 the transfer lasted from minor cycle (m + W + 2) to (m + T + 2). Alternatively, if the characteristic was 1, the transfer lasted for one minor cycle (m + W + 2) and for two cycles (m + W + 2) and (m + W + 3), if the characteristic was 3.

Conditional branching, also known as discrimination, was based on functional destinations 24 (negative) and 25 (zero). If the source-destination pair of 15-24 was specified, then if the contents of TS15 were positive, control passed to the instruction at m + T + 2, when the current instruction completed, otherwise it passed to the instruction at m + T + 3.

Trigger setting TCA was activated using a single cycle transfer to destination 21 and deactivated using a transfer lasting more than one cycle. When TCA was on, TS20 held the contents of DL10 delayed by one minor cycle i.e. 10₅ could be obtained in cycle 6 from TS20. This could be used, by specifying the transfer 20 – 10 for 32 minor cycles, for saving all the words in DL10 one position back.

A single cycle transfer to destination 23 from any source, switched trigger TCB on and caused DS14 to behave as two single length stores rather then one double length store and only reverted when a multiple cycle transfer was made to destination 23.

Multiplication required that TS20 held the multiplicand and the multiplier was held in the odd word of DS14 and 0 in the even word and a transfer made to destination 19. The product then appeared in DS14 in 65 minor cycles. The multiplier and multiplicand were treated as positive numbers and extra programming was required for signed multiplication. Other operations could execute while multiplication is proceeding. TCB had to be off, when the multiplier was in use.

A transfer of more than one minor cycle made from any source to destination 0 caused the contents of the source specified to become the next instruction rather than the instruction specified in the next instruction field. This was used in instruction modification.

Input was achieved through a card reader and front panel switches and output was through the card punch and front panel display lights. A number set up on these switches was held in a location known as the Input Dynamiciser Source (IDS), and converted to a serial form suitable for the delay line memory, when source zero was specified. The contents of the IDS were available from source 0 once every 32 microseconds. A card feed was initiated by the use of destination 31; specifying that the IDS provided the number available at the reading brushes rather than that set on the switches. Read instructions were normally coded as stopping instructions, with each row the card passing under the brushes triggering a signal. When a card had passed through the reader, source 0 reverted to the IDS.

The 32 instructions that could be held by delay line were punched on three cards (known as a triad), using the first four rows at the top of the triad to direct the computer where to store the instructions being input.

Destination 28 was known as the Output Staticiser (OPS) which could be switched from a set front panel of lights to the punch magnets, using a transfer to destination 30. The 32 punch magnets were used to punch in the first 32 columns of a card. Synchronisation was again achieved using a stopper technique. Computation of could be executed between rows of cards being read or punched.

In February 1954 a drum was added, initially holding 32 tracks, each containing 32 words; it used two moving groups of 16 heads, one for read and one for write operations. The drum was accessed using destination 22 and each operation required two instructions: first the heads were positioned using a source address of 16 or 17 and then the head to use specified by a source in the range 0 to 15 of a subsequent instruction. Specifying a characteristic of 0 selected the read heads and 1 the write heads. All transfers took place to or from DL9 and took about 11 major cycles.

DEUCE

DEUCE’s storage was sequentially numbered, as shown in table 3. The bulk of the storage was provided in the form of 12, 32-word long delay lines DL1-DL12. It had four temporary (short) registers TS13, TS14, TS15, TS16, two quadruple length registers QS17 and QS18, and three double registers DS19, DS20 and DS21.

The machine also had an unsigned multiplier and a signed divider. The divisor was placed in TS16 and the dividend in the odd cycle of DS21. After the operation, which took 66 minor cycles to complete, the quotient is in the even part of DS21 and the remainder was in the odd part. The instruction to divide was given by 1-24. Once the divide had completed the remainder needed to be adjusted, to give the correct value.

The format of the instruction word was identical to Pilot ACE except the Timing bits were in locations 26-30. It was possible to index through an array by increasing the wait count by 1 each time through a modified instruction. However, if the Joe digits (the four digits between the W and T instruction fields) were set to 15, once W exceeded 31, further increments were propagated through to the timing field, making the next instruction one step later than originally specified (similar to taking a different action when a counter expires – Pilot ACE could achieve this using instruction bits 22-24).

Table 3 - Source and destination interpretation for DEUCE

As table 3 shows, DEUCE made use of functional sources and destinations, with some differences from Pilot ACE. For example, functional destination 22 added the contents of the source variable to DS21, whereas destination 23 provided an additional function subtracting the source from DS21. Similarly for short registers; addition and subtraction used TS13, left and right shifts used TS14; TS14 and TS15 were used for logical AND and exclusive OR operations. Discrimination was enabled using destinations 27 (+ or -) and 28 (zero). Destination 24 triggered one of the operations shown as “triggers” in table 3.

The interpretation of the W and T fields were as for Pilot ACE, but a characteristic of 0 initiated a single word transfer, 1 a long transfer and 2 a double word transfer. The same address modification techniques used by Pilot ACE could be used by DEUCE.

The magnetic drum could be addressed using one four-bit field referencing either the read or write head. Destination 30 specified which of the 16 blocks of read or write heads were used and destination 31 specified which head in the block to access, with the characteristic specifying the operation (even=read, odd=write. It took 13 major cycles to complete a write). DEUCE’s primary I/O mechanism was 80-column punched cards; all machines being capable of using 32 of the 80 columns directly and some being able to use 64 of the 80 columns directly (requiring the IDS and OPS to be 80 bits wide). DEUCE could be fitted with paper tape equipment; the reader speed was 850 characters per second, while the paper tape output speed was 25 characters per second.

DEUCE came in two main forms; Mark I, seen as a scientific machine and Mark II regarded as a data processing machine. Mark II provided a combined IBM 528 card reader and punch, which could read cards at 200 per minute, and punch at 100 cards per minute. English Electric introduced the Automatic Instruction Modifier (AIM), which used either QS17 or QS18 as the source and 0 as the destination, within a few months of DEUCE’s initial release in 1955. Both Mark I and Mark II could be provided with a magnetic tape option.

The Mark IIA machine could have seven extra delay lines (numbered 1A to 7A) and their use enabled by setting the instruction P1 digit to be on and disabled by setting it to zero. Transfers between the additional and standard lines had to be made via an intermediate storage location. To address a next instruction located in one of the additional lines required trigger TCC to be set using instruction 14 - 24 with a characteristic of 1.

MOSAIC

Mosaic was described in detail in Resurrection 101. It had a 40-bit word (as shown in figure 3) and had 63 long delay lines, 28 short delay lines and four double word addresses. There were 16 minor cycles in a major cycle. Delay line numbers greater than 96 were used to specify special addresses used for input and output, discrimination tests and a number of constants. Discrimination worked in a similar manner to the way it did in Pilot ACE.

MOSAIC was a four-address machine, with a single instruction being capable of addressing two source operands, a destination operand and the next instruction simultaneously. Further, there was a separate function field to specify the operation being executed. The number of bits for addressing was 7 and the number of bits allocated for the Next Instruction Source was 5 i.e. 31 delay lines could be addressed. A next instruction field of zero specified that the next instruction should be extracted from short register zero, enabling modifying an instruction can be carried out using a short register, making it independent of machine cycle and therefore easier to program.

MOSAIC offered signed and unsigned multiplication options through a separate multiplier with a multiplication requiring 83 minor cycles to complete. It had a separate delay unit which allowed right shifts, i.e. multiplication by powers of 2 to be achieved.

Figure 3 - the MOSAIC Instruction word

Figure 4 – MOSAIC schematic

It utilised only one timing control, which was associated with four modes of characteristic setting:

• Transfer started with the first obey cycle and ended when the timing count expired.
• Transfer occurred only at the point the timing count expired.
• Forced discriminate, where transfer started during the first obey cycle, ended when the timing count expired and a further minor cycle inserted, before the next instruction was fetched.
• An execution time of exactly one major cycle with transfer occurring only at the point the timing count expired.

MOSAIC did not support a magnetic drum, although data could be captured on punch cards as temporary intermediate storage. Input into MOSAIC was primarily through punched cards and output could be through either punched cards or an electric typewriter, although the latter was a very slow device. A simplified schematic for MOSAIC is shown in figure 4.

The first thing to note is that each process (Virtual machine (VM) in the jargon) has its own address space of 2³¹ bytes plus access to a further 2³¹ bytes of public (i.e. shared) store. Think of it as a garden fork. The tines representing the local store of each VM and the handle representing the public store. The 32-bit address is divided into four zones –

• The top bit tells the hardware or microcode whether the access is for the VM’s local store (0) or for the public store (1). So far, so Atlas 1.
• The next 13 bits describe a segment. It is not immediately obvious what the notion of a segment is for, but it is important and we’ll come back to that in a few moments.
• The following eight bits describe a page. This is what you think it is. A page of store can either be in main (semiconductor) store or the page can be on disc in which case, it will be fetched back into main store and matters will proceed as if nothing has happened.
• The final 10 bits describe the offset between the start of the page and the required byte address.

Each VM had access to two pointers, one to the public segment table and the other to its particular local segment table. A segment table is a vector of pointers to sets of page tables and these in turn point to the real address of a page of store or a disc location depending on whether the desired byte location was in main store or not. None of this was visible to the user’s running program being buried deep within the hardware, microcode and the operating system. I am given to understand that, at some stage in the 1990s, as the cost of semiconductor store had reduced and the sizes of stores had consequently increased, the page size was increased. But this was after I had ceased contact with VME and the details escape me.

But what is the point of the segment? Well segments also carry properties which are inherited by the underlying store. Let’s start with an easy one. Our first segment property is the Execute Permission Bit. If set then this means that the underlying store locations are all instructions. But if the bit is clear then they are data items. The Order Code Processor (OCP) will refuse to execute an instruction where the bit is unset and will immediately fail the process.

Now let’s dive a little deeper. The Order Code Processor (OCP) has within it a 4-bit register known as the Access Control Register (ACR). The ACR value varies from 0 to 15 and when an attempt is made to access a location in the store, the ACR is compared with the owning segment’s Read Access Key (RAK) and Write Access Key (WAK) (both 4-bit properties). This determines whether the requested access is allowed. A Low ACR means that the OCP is currently very privileged, a high value, less so.

These segment properties and the matching OCP registers are essentially debugging aids which bring a process to an immediate fault exit if the tests forbid the requested store access, rather than when the effect of the error is manifested which latter is likely to be very difficult to diagnose.

If all this reminds the reader of Multics, then that is not a co-incidence.

To complete the picture, we should add to public and local store a third type – “global store”. Global store is store which is shared between two or more VMs but not all of them. Global store is implemented as local segment tables pointing to public page tables. It’s most often used by Transaction Processing Monitors and Database Management Systems where efficient coordination and data sharing between VMs is needed.

With luck, I’ll build on the information here in the next edition of Resurrection.

Argus 700S on the way: The first Ferranti Argus 700S minicomputer configuration for the data communications network to link British Steel’s four DP centres and 10 production sites in the UK has been delivered to Leasco Software at Maidenhead for program development work. The 700S will form the network operations installation and is scheduled for British Steel’s new bureau at Rotherham where it will provide a man/machine interface to the network. In all, Ferranti will be supplying 23 Argus configurations to British Steel under a £4.5 million contract. A £1.5 million slice of this is allocated to Leasco, Ferranti’s main subcontractor, who will be writing the network software in Coral 66. The hardware includes the Argus 700S with 128K words of core memory, two Megabytes of fixed head disc storage and 20 Megabytes of cartridge disc storage. (CW 461 4/9/1975 p1)

Training simulator for nuclear plant: A nuclear power plant operator training simulator is to be supplied to the Virginia Electric and Power Co, Vepco, by Electronic Associates Inc of New Jersey. Valued at more than $3 million, the simulator will be installed at Vepco’s Surry nuclear power station, about 75 miles from Richmond. The EAI system will be based on two System 32 medium scale computers from Systems Engineering Laboratories, which will store mathematical models of equations and parameters concerning both normal and abnormal operating situations. Under the control of an instructor, the system will respond to an operator’s inputs via the mathematical models which will be used to represent the operations of each segment of the actual plant. In addition, the simulator will be used to give periodic retraining courses necessary to requalify experienced operators. Other applications will include operating procedures development and verification. (CW 462 4/9/1975 p39)

UK PoS system for European market: Seeing a big potential market among cash and carry wholesalers all over Europe for purpose-built interactive point of sale terminal systems, a UK minicomputer systems house, Real Time Controls, has produced an inexpensive system for which major orders have already been placed by one of the biggest cash and carry firms in the UK, Nurdin Peacock. Real Time Controls has been involved with minicomputer and terminal systems since it was set up five years ago, and has worked closely with Honeywell on many Series 16 mini systems development projects and contracts throughout Europe. However, RTC decided to go to an independent supplier, Data General, for the mini to control its cash and carry system. This is the Nova 2/10, which provides three of the most valuable features of the system, on-line multiple VAT rate calculation and invoice printing, on-line price ticket printing for goods inwards and on-line price validation for goods going through the checkout, something that could save a cash and carry warehouse as much as £100,000 a year by preventing wrong input of prices at the checkouts. (CW 462 11/09/1975 p56)

Low-cost OCR data capture: Low-cost OCR data capture is provided by three page-readers, the Bardata OCR 10, 20 and 30, built in the US by the Datatype Corp of Miami, Florida, and now available in the UK from British Airways at prices starting at £4,300. The three readers employ the same data capture technique as the two Bardata readers already sold by British Airways, the DFR 400 and DFR 500. The Bardata machines read a compact barcode printed just beneath each of the eye-readable characters. A Bardata machine can read these barcoded characters at up to 110 chps, and incorporates a microprocessor which enables it to be programmed to carry out a wide variety of editing and checking functions. (CW 463 18/9/1975 p20)

Police get Collator machine: After six days of acceptance trials, the Honeywell 6025 chosen for the Thames Valley Police’s Collator Project has now been handed over to the Home Office. The trials were carried out by the Technical Services Division of the Central Computer Agency. The Scottish-built 96K computer was ordered a year ago and cost £500,000. Installed near Oxford, it will be used for a crime information collation and handling application which is to be carried out by the Police Scientific Development Branch in conjunction with Thames Valley. The aim is to evaluate crime data handling methods with a view to recommending techniques that could be applied more generally. VDUs will be used to enter, retrieve and handle data and some of these will be located in police stations in the Thames Valley area. (CW 463 18/9/1975 p20)

Micro based on GIM’s CP-1600: A microcomputer system based on the CP 1600 microprocessor introduced by General Instrument Microelectronics earlier this year has been announced. Known as the GIC 1601, a typical system with 8K 16-bit words of RAM and 3K words of ROM memory costs £1,379. In addition, the purchase price includes full software support. A user is supplied with operating system, assembler, text editor, relocatable linking loader and diagnostic programs on paper tape, together with listings for binary maths routines and code conversions for incorporation in user application programs. General Instrument is also offering the individual cards already tested and debugged. Customers can buy the computer card, an I/O card and a console interface card incorporating a microprogrammed operating routine. The basic 8K RAM memory may be expanded to 65K. The microprocessor card alone costs £213 reducing to £106 for quantities of 100 or more. For assembling a system from the MOS chips, the CP 1600 microcircuit can be purchased for £127 reducing to £69 for quantities over 100. Hardware and software manuals are available at a cost of £5 each. The CP 1600 family includes the microprocessor, the 1630 series of 1 Kbit static RAMs for variable data storage and the 1620 series of four 16K ROMs for microprogram storage. General Instrument reports that additions to the family are already planned. (CW 464 25/9/1975 p39)

Viewdata to be based on GEC 4080: Although news of the Post Office’s latest telephone information service has been in the air for some time, the capabilities of this new interactive system were not made known until this week at the Eurocomp conference. At the same time an order for a GEC 4080 computer, on which the Viewdata system will be based, has been placed by the Post Office. The service, which is called Viewdata, will permit a wide range of information to be called up over the public switched network and displayed on a modified television set, accessible by means of a hand-held keypad. Alternatively, a purpose-made Viewdata terminal will also be available to commercial users, with built-in control and telephone. The service will differ from the BBC’s Ceefax and the IBA’s Oracle services in that it is interactive, and will permit simple messages to be transmitted to users. (CW 464 25/9/1975 p40)

Univac’s bid for the middle market: Downward extension of Univac’s new 1100 computer series has come about with the expected arrival of the 1100/10, which was launched yesterday at Datafair. A magnetic tape subsystem, the Uniservo 14, has also been announced for the series, and for 90/30 users there is a new disc drive. The 1100/10 is likely to be the lowest entry system in the medium-to-large-scale series, which already includes the 1100/20 and the 1100/40. It is simply a smaller version of the existing machines, utilising the same peripheral equipment, communications subsystems, and software. In price, it competes with the IBM 370/135, the ICL 1903T and the Honeywell 66/20, but Univac claims that the 1100/10 gives greater performance than a 370/145, 1904S or, 66/40. The computer is not aimed at replacing any current model, says Univac, but as it gives more power than an 1106 for less money, it is improbable that Univac will sell anymore 1106s. The 1100/10’s main memory can be expanded from the basic 128K words to 512K in 128K modules. Alternatively, a 256K starting module can be augmented to 512K with the addition of a single module. The system is said to achieve an average execution time of 1.468 microseconds at 0.68 million instructions per second, and can be upgraded to an 1100/20. (CW 465 2/10/1975 p3)

Sea Harrier system: Under a £1 million contract from the Ministry of Defence, the inertia systems department of Ferranti in Edinburgh is to develop a heading and attitude reference system, HARS, for the Sea Harrier aircraft. HARS will also provide data for the aircraft’s weapon aiming system. The system will be based on a stable platform similar to the existing Ferranti inertial navigation platform. In addition, it will utilise two oscillo-gyro-scopes and three accelerometers together with a mysterious “digital sensor computer”, DISC. A spokesman for the company could disclose few details of the DISC unit, except to say that it was fed heading attitude and velocity signals from the platform and velocity data from a Doppler system. First development models of HARS are scheduled for next autumn. (CW 465 2/10/1975 p7 )

EMI wins £2m NHS order for scanner: A world leader with its computer-controlled brain scanner system, EMI has scored its latest sales success in the UK, securing an order for 15 systems, worth £2 million, from 15 hospitals in England and Scotland. Meanwhile, in the US, where 200 of the 250 scanners sold to date by EMI have gone, the company has set up a company, EMI Medical Inc, in Chicago to specialise in marketing the scanner. EMI Medical is formed from a division previously known as EMItronics Inc, and is part of EMI Technology Inc, set up to unify all EMI electronic interests in North America. In the UK and the rest of Europe, scanner sales will now be handled by an autonomous company within the EMI group, EMI Medical Ltd. Total sales of EMI-Scanners to date amount to £40 million, of which £38 million worth have gone for export. EMI estimates that the world market for scanners will be worth £100 million a year by 1980, and it includes body scanners in that figure. EMI has produced a prototype body scanner, based, like the brain scanner, on a Data General mini, and the system, called the C 75000, is currently being field tested at the Northwick Park Hospital at Harrow, Middlesex, and at the Mayo Clinic, Rochester, Minnesota. (CW 466 9/10/1975 p4)

Micro family from Texas Instruments: A family of 16-bit microprocessors and microprocessor-based computers, together with fully compatible software, has been announced by Texas Instruments. Known as the 990/9900 family, the units were developed at the company’s Houston location and are scheduled for first deliveries in the UK from next March onwards. On a separate front, Texas Instruments is to introduce the industry’s first 16K-bit RAM next summer. The total world micro/minicomputer market over the next 10 years has been estimated to be worth some £15,000 million with 16-bit processors taking the largest slice, says Texas. In introducing its TMS 9900 third generation NMOS microprocessor, Texas is expecting the unit to become the industry standard through the 1980s. The 990/9900 family is initially to comprise the TMS 9900, the Model 990/4 microcomputer and Model 990/10 minicomputer. In addition, there are software development systems, a prototyping system and cross support software on the CSS International, Tymshare and Honeywell Mark III time sharing networks. (CW 467 16/10/1975 p3)

Alternative memory system: A memory system designed to be cheaper, faster and more reliable alternative to drum and disc storage systems is now available in the UK from Intel. Known as the in-65, the one Megabit unit is based on Intel’s 2416 16K charge coupled device. The in-65 is made up of three boards, namely the memory unit, a control unit and a buffer unit. The memory unit can be organised in 128K words by eight or nine bits with a total capacity of 1,179,648 bits, and the system can be expanded by combining memory boards. Each buffer unit is capable of driving up to eight memory unit boards. It is possible to expand the system from 9 to 18-bit operation, enabling a 1,024K by 18-bit world device, for example, to be constructed. Such a unit would incorporate 16 memory unit boards. (CW 467 16/10/1975 p31)

ICL goes for the small systems market: In a bid to win a share of the potentially lucrative market for small business systems, ICL plans to launch a machine known as the 2903/20 next month. Aimed essentially at the small, first-time users, the new system is a considerably scaled down version of the highly successful 2903, which now gets the designation 2903/40. It is just a year since ICL introduced the large 2900 machines, and the announcement of the 2903/20 at the end of November will coincide with installation and commissioning of the first 2970s. So far, few details about the 2903/20 are available. (CW 468 23/10/1975 p1)

Plessey building £2m ATC radar project: A major air traffic control contract, involving some 60 Digital Equipment PDP-11 minicomputers, and worth £2 million, has been awarded to Plessey by the Civil Aviation Authority. The contract is for a Processed Radar Display System, PRDS, to interface the air traffic controller’s displays to the central IBM 9020D system at West Drayton, and follows an evaluation contract placed with Plessey some two years ago. Implementation of the system began in May, and will take about 18 months to complete. Plessey is due to hand it over early in 1977, and the Civil Aviation Authority anticipates that it will take about a year of further development and testing before the system goes into full service. Primary and secondary radar data giving details of aircraft flight paths, call signs and heights from six enroute radar stations will be fed to the 9020D, and the purpose of the PRDS is to take this information from the mainframe complex and process it into a form suitable for display on the high-definition screens used by the traffic controllers. (CW 468 23/10/1975 p40)

On-line TOPS keeps the freight trains rolling: One of the most extensive and comprehensive computerised freight management systems in the world is now fully operational. This week British Rail officially inaugurated its Total Operations Processing System, TOPS, on schedule, four years after placing the first contracts. TOPS is an on-line real time system based on an IBM 370/168 at Marylebone, London, linked to 200 centres within British Rail’s 11,500 route mile national network. The system provides information on the whereabouts of the 303,600 wagons in the authority’s fleet. including such details as whether loaded, empty, moving, contents, point of origin and destination. When the project was initiated a budget of £32 million was allocated until 1980. So far, just over £16 million has been spent. Early predictions by British Rail of the benefits that will accrue from TOPS look like being achieved. (CW 469 30/10/1975 p11)

Program to combat oil spillage: A program designed to fill an important role in protection of beaches and seas against oil spillage has been demonstrated in London to the International Government Maritime Consultancy Organisation (IMCO), a branch of the United Nations. The software was developed by the Canadian Department of the Environment, in collaboration with APL time sharing specialist I. P. Sharp Associates, and was run from London through Sharp’s Toronto based network. Known as Neels (National Emergency Equipment Locator System), the program in its present form controls a database of locations throughout Canada where oil-controlling equipment, ranging from detergent to physical barriers, is stored. Given the location of an oil spillage, the nearest stores of appropriate equipment can be easily identified. There would obviously be little difficulty in extending this system outside Canada, and eventually setting up a worldwide database, provided a significant number of bodies volunteered information. The UN body was reported to have shown interest in such an idea. (CW 470 6/11/1975 p9)

Honeywell Hiway for process control: A new control system architecture has been announced by Honeywell which offers a considerable extension of the principle of distributed processing in the field of process control. Called TDC, for Total Distributed Control, the system includes a wide variety of microprocessor-based hardware modules, and the first package of hardware and system software has been announced as the TDC 2000. The system, developed over five years in the US, Canada, Japan and the UK, is built around the General Instruments CP 1600 16-bit microprocessor, which was designed specifically to meet Honeywell’s requirements. The key elements of the system are a universal coaxial cable link dubbed by Honeywell a “Data Hiway”, and microprocessor driven controllers and VDUs. The TDC 2000 can be combined with process control minis such as Honeywell’s HS 716 and HS 4400, and the “Hiway” makes for big savings on wiring costs. The CP 1600-based controller allows push-button selection of functions, and uses digital methods in applications where analogue instruments are used at present. The data path is automatically controlled by a device called the “hiway traffic director” and overall systems control is provided by grouping three VDU operator stations together. The elements of the system are designed to plug in to the “privacy”, eliminating the need for electrical connections. (CW 471 13/11/1975 p1)

EIN packet switching accepted: The packet switching system for the European Informatics Network, EIN, passed its acceptance tests on time on November 3rd. The system, designed by Logica of the UK in conjunction with SESA of France, was designed around CII Mitra 15 minis under a fixed price contract with the European Commission. The packet switching systems are to be installed at the five nodes at present planned for the network, at NPL in London, Iria in Paris, the Euratom site at Ispra in Northern Italy, and research and educational institutions in Milan and Zurich. The tests involved connecting two packet switches via a 48K-baud link, and the next phase in the project will involve getting the nodes running. SESA and Logica are developing the software for the network, and also designing High-level Data Link Control line interface hardware. Further nodes may be added to EIN in the future, and one site under consideration is CERN, the European centre for nuclear research on the Franco-Swiss borders. (CW 471 13/11/1975 p1)

HP’s data station: Described by Hewlett-Packard as a mini data station, its model HP 2644A is a VDU terminal capable of carrying out program preparation, editing, tape copying and tape-to-printer operations. The terminal incorporates 230,000 bytes of built-in mass data storage and two integrated tape transports, which will use the latest 3M mini cartridge, a storage medium that is something of a novelty in itself. Said to have resulted from close cooperation by Hewlett-Packard and 3M, the mini cartridge in use with the 2644A records 115,000 bytes of serial information on the cartridge’s 140 feet of tape. A wide range of functions are possible on the new mini data station, both on-line and off-line. Forms can be easily compiled by means of the special character types for simulated graphics. These forms can be held on cartridge and retrieved at high speed, estimated average access time being 10 seconds. Off screen storage facilities permit the use of forms over 24 lines in length with facilities for scrolling, page select and tabulation. It has a number of editing capabilities including character line insert and delete. Cursor sensing and positioning can also be carried out. The terminal is sold as a single unit at a price of £3,000, and with the option of additional character sets at £3,360; in quantities of six, the terminal will cost from £2,600. Price of the new mini cartridge is £7, almost twice as much as the conventional cartridge. However, it is said to have an exceptionally low error rate. (CW 472 20/11/1975 p46)

IAL system to control networks: Operators of various sized networks are offered a Medius modular data communications control system by International Aeradio Ltd which has automatic line switching, monitoring and testing capabilities. Lloyds Bank is installing the first big system, which it commissioned last year, before the system was christened Medius. Medius hardware comprises three main modules, all based on what IAL describes as a family of compatible PC boards and sub-assemblies, each one designed to perform a different control or switching function either locally or remotely. One unit, called the peripheral module, can be located anywhere in a network and performs switching, monitoring and looping functions. A medium peripheral module capable of handling 16 V24 lines measures eight inches high and can be housed in a standard 19” wide rack. Operators of small networks can install and manually operate the peripheral module as an independent unit. Bigger networks require several peripheral units to be linked to a local controller, called the system module, which would in turn be linked up to a Master Control Module, MCM, located at the mainframe site, to form a complete hierarchical network control system. The MCM can be a custom-built hardwired unit, offering terminal address translation facilities in its more sophisticated versions, such as the system being installed by Lloyds at its London computer centre. (CW 472 20/11/1975 p46)

Triad to market the NPL Scrapbook system: Many ingenious software products are hatched quietly within government and university research departments and are regrettably never commercially exploited. As a refreshing exception to this rule, the National Physical Laboratory’s novel Scrapbook textual information handling system is now to be generally released through Triad Computing Systems. The software has already gained one prestigious user, the National Water Council, and could possibly be another contender for the House of Commons information retrieval project for which tenders are expected to be invited soon. Triad is working on an appropriate “commercial” version of Scrapbook, to operate on a stand-alone Computer Technology Modular One. The NPL’s original implementation was designed to work in connection with its own network software. Other Triad improvements will be in the security and recovery areas. The company has, however, the right to sell the original version and such other tailored versions as users may request. The appropriately named Scrapbook is basically a storage and retrieval system for passages of unformatted text. It has been in use within the NPL for over two years, and is now accessible through a network of visual display terminals extending to most of the laboratory’s departments, and based on two Modular Ones. Text passages, each consisting of one or more VDU “pages” are stored and retrieved according to user-specified keys. One passage may be linked to a number of others via additional keys. Thus, a passage may include a questionnaire allowing the immediate retrieval of further relevant text according to the user’s reply. Such a strategy, Triad points out, lends itself to a variety of information retrieval applications. (CW 473 27/11/1975 p9)

On-line banking by CMG: One of the biggest UK based service bureaux, the CMG Group, is now offering a comprehensive on-line processing service, INTABS, International Terminal Accounting and Banking Service, to the London branches of Continental banks. CMG also intends to link the London banks to their head offices on the Continent via the SWIFT international funds transfer network when it goes live next year. CMG reveals that 20 big Continental banks are already seriously interested in INTABS, which can handle current account and foreign exchange transactions in real time, as well as loan and deposit processing and general accounting work. Depending on their size, clients could install a Burroughs TC 500 intelligent terminal and B771/772 RJE system, linked online to the CMG bureau centres at Croydon or Greenford, Middlesex, both of which have Burroughs B4700 mainframes. (CW 473 27/11/1975 p9)

Country-wide TP service planned:

A teleprocessing service being set up as a joint venture by J. Lyons, Lucas Industries and Computer Resources Ltd, could soon be the largest TP bureau operation in the UK. It is based on a formidable line-up of IBM mainframe hardware at two big centres. The smaller centre, in London, is based on the Lyons 1.5 Megabyte 370/155, with 14 100 Megabyte disc drives, supporting batch, RJE and TSO processing. The bigger centre, at a Lucas Industries site in the West Midlands, has three 370/158 computers, one with two Megabytes of main memory, and the other two with 1.5 Megabytes each. The three processors share 46 100 Megabyte disc drives and 20 3420 tape units. This centre is devoted exclusively to time sharing and batch work generated on an RJE basis. Computer Resources believes that this total dedication to teleprocessing is unique in the UK. The consortium expects to win a lot of business from existing users of medium sized computers and sees them using the West Midlands bureau as a more cost-effective alternative to upgrading their in-house systems. In addition, it believes that the size of the joint facility could attract interest from companies needing guaranteed and substantial back up as an insurance against any protracted failure of their own systems. CRL also believes that the majority of TSO business will come from mainframe users who are running expensive and awkward time-sharing operations alongside batch work. (CW 474 4/12/1975 p1)

EMI updates scanner: A new version of EMI’s revolutionary brain scanner, claimed to be four times faster than the original model, has been announced by the company. At the same time EMI has revealed that sales of its CT 5000 general purpose scanner, introduced in April, have shot up from 16 at the beginning of November to 40. With a total value of over £10 million. Whereas the original scanner was built around a Data General Nova minicomputer, the new model, the CT 1010. incorporates the Eclipse. It has two scanning speeds, enabling it to carry out a scan of a patient's brain and neck in one minute or four minutes. The earlier model had a four and a half minutes scan cycle. The CT 1010’s new scanning unit allows patients to be handled more easily. The basic price of the CT 1010 is about £180,000, which is only marginally more than the £165,000 price tag on the original version, which brought in over 360 orders worth £60 million, most of them from overseas. The CT 1010 will supersede the original scanner, and already EMI is slowing down the production of the older model. Most of the orders for the CT 5000 general purpose scanner, which is also based on the Data General Eclipse, have come from the US. This scanner cost about £250,000, and can perform a scan in 20 seconds. (CW 474 4/12/1975 p3)

Asas to analyse stresses in North Sea oil rigs: A further accolade has been given by the government to the research and development division of consulting engineers W. S. Atkins and to its Asas structural analysis program. Atkins has been engaged, under a contract of undisclosed value, to analyse stresses in the joints of North Sea oil rigs, as part of the government-sponsored Offshore Steel Research project. Asas has already obtained government recognition in the shape of a development grant under the Department of Industry’s software products scheme. The latest contract may also have the effect of enhancing the product since, as part of its work, Atkins has been commissioned to add a visual display interface. This new software will enable a user to enter basic details of the geometry of the joint under study, a view of which will be displayed. Such specifications as the division of the structure into appropriate finite elements will then be input interactively and, when information is complete, Asas input parameters will be automatically generated. Results of the Asas analysis can also be displayed in graphic form. (CW 475 11/12/1975 p8)

Interface provides a taste of EPSS: An ICL interface unit for linking to the Post Office’s Experimental Packet Switched Service, and a Ferranti Argus 700S, which is being used in a job control language study project, are two new pieces of hardware which have just been installed by the National Computing Centre in its new Manchester headquarters. The ICL interface, which has the model number 8790, is built around the company’s 7503 intelligent remote job entry terminal. The NCC has a 32K 8790 equipped with a tape cassette unit for program loading, and a special circuit board which enables it to link four mainframes, via a 2,400 baud line, to the EPSS exchange in Manchester, which is equipped with Ferranti Argus 700Es. The 8790 was bought with part of the NCC’s grant from the Department of Industry at a cost of around £19,000. In addition to linking its own 1905F to EPSS, the NCC is making the 8790 available at a nominal cost to any of its members who wish to try out the network. In this way, the NCC expects to be able to gather information on the performance of EPSS. (CW 476/7 18-25/12/1975 p11)

Members and others are welcome to attend CCS Seminars and these are also available via Zoom.

London Seminar Programme

London meetings take place at the BCS – 25 Copthall Avenue Moorgate EC2R 7BP starting at 14:30. The venue is near the corner of Copthall Avenue and London Wall, a five minute walk from Moorgate Station and 10 from Bank.

You should use the BCS event booking service to reserve a place at CCS London lectures. Go to www.computerconservationsociety.org/lecture.htm. The service must be used both for attendance in person and for remote attendance.

For queries about London meetings please contact the CCS meetings secretary Roger Johnson at meetingssec@computerconservationsociety.org.

Manchester Seminar Programme

Manchester meetings normally take place at The Manchester Metropolitan University, Chester Street, Manchester, M1 5GD – Room E0.05 in the John Dalton East Building starting at 18:00 (but see the description of specific lectures on the CCS website as building work is currently underway).

Details are subject to change. Members wishing to attend any meeting are advised to check the events page on the Society website.

SIM : Demonstrations of the replica Small-Scale Experimental Machine at the Science and Industry Museum in Manchester are run every Wednesday, Thursday and Friday between 10:30 and 13:30. Admission is free. See www.scienceandindustrymuseum.org.uk/ for more details.

The National Museum of Computing : See www.tnmoc.org/days-open for the opening hours schedule. Situated on the Bletchley Park campus, TNMoC covers the development of computing from the “rebuilt” Turing Bombe and Colossus codebreaking machines via the Harwell Dekatron (the world’s oldest working computer) to the present day. From ICL mainframes to hand-held computers.

Please note that TNMoC is independent of Bletchley Park Trust and there is a separate admission charge. Visitors do not need to visit Bletchley Park Trust to visit TNMoC. See www.tnmoc.org for more details.

Science Museum :

There is an excellent display of computing and mathematics machines on the second floor. The Information Age gallery explores “Six Networks which Changed the World” and includes a CDC 6600 computer and its Russian equivalent the BESM-6 as well as Pilot ACE, arguably the world’s third oldest surviving computer.

The Mathematics Gallery has the Elliott 401 and the Julius Totalisater, both of which were the subject of CCS projects in years past, and much else besides.

Other galleries include displays ranging from ICT card-sorters to Cray supercomputers. Admission is free. See www.sciencemuseum.org.uk for more details.

Bletchley Park : Exhibition of wartime code-breaking equipment and procedures plus tours of the wartime buildings. Go to www.bletchleypark.org.uk to check details of times, admission charges and special events.

Other Museums :

At www.computerconservationsociety.org/museums.htm can be found brief descriptions of various UK computing museums which may be of interest to members.

Computer Conservation Society

Aims and Objectives

The Computer Conservation Society (CCS) is a co-operative venture between BCS, The Chartered Institute for IT; the Science Museum of London; The National Museum of Computing (TNMoC); and the Science and Industry Museum (SIM) in Manchester.

The CCS was constituted in September 1989 as a Specialist Group of the British Computer Society. It is thus covered by the Royal Charter and charitable status of BCS.

The aims of the CCS are:

• To promote the conservation of historic computers and to identify existing computers which may need to be archived in the future,
• To develop awareness of the importance of historic computers,
• To develop expertise in the conservation and restoration of historic computers,
• To represent the interests of Computer Conservation Society members with other bodies,
• To promote the study of historic computers, their use and the history of the computer industry,
• To publish information of relevance to these objectives for the information of Computer Conservation Society members and the wider public.

Membership is open to anyone interested in computer conservation and the history of computing.

The CCS is funded and supported by voluntary subscriptions from members, a grant from BCS and by the free use of the facilities of our founders. Some charges may be made for publications and attendance at seminars and conferences.

There are a number of active projects on specific computer restorations and early computer technologies and software. Younger people are especially encouraged to take part in order to achieve skills transfer.