Elliott 803, 903 & 920M — Terry Froggatt

TNMoC 803

Peter Onion reports that the 803 is running happily.

TNMoC 903

Peter Williamson, Kevin Cooper, and I met at TNMoC recently with the intention of “fixing the 903 punch”. Our first step was to reconnect the Accumulator Monitor Unit, which has been disconnected for some five years. This showed that the punch demand signal was correct. We could not test the punch circuitry by swapping in a known good punch, because the TNMoC punch has a round connector, not Elliott’s usual Centronics 24-pin or HMS Dryad’s D-25-pin connector. Our next step was to ring through the cable, between the known paper tape station pins and the unknown pins on the round connector. When we carefully replaced this cable, ensuring that some loose pins made good contact, the punch sprang into life. Finally, we successfully ran the X10 random-speed reader & punch test.

Six Elliott 920Ms for Jaguar XX764

Neil Atterbury is having an XX764 open house day at Enstone on 15^th of August, and he says that “my Elliott friends” will be welcome. See www.ccsoc.org/ell0.htm.

In the previous Resurrection I described how Erik Baigar and I had visited Neil and his Jaguar at Enstone last October to run some 920M code in the aircraft. We started cautiously, being aware that rogue power from the aircraft might harm a 920M. 920M 5355 was known to have store fault (with a 50% chance that the presumed faulty diode would be unreachable), so we chose to use this 920M (with code written to avoid the store potholes) to check the power, which was OK. We then checked three other 920Ms which had worked at home: 385 & 5357 were OK in the aircraft but 5360 tripped the aircraft power.

So earlier this year (at home), I took a closer look at the faulty 920Ms. Removing the top & bottom covers is easy, but removing the end-plates (so that the unit can be opened up into the Z-shape shown in the sales literature) requires removing 22 bolts (straightforward) and 24 small countersunk screws (on average two needed to be drilled out).

We knew that 920M 5360 (which tripped the power) was missing one power connector pin, which was known to be one of many ground pins. I also found that another pin had been bent (at Enstone), which I’ve since straightened. The missing pin is specifically ground for the “+5v aux” power supply, and it is commoned with other grounds in my test rig. My guess is that it is not commoned with other grounds within the aircraft, which would leave the +5v aux itself floating and unused.

Regarding the other two 920Ms, I’ve been able to repair 5356 which I’ve previously reported as “blowing my fuses”, by replacing the type 30F store module at P02 by a module borrowed from my own 920M 5343. The remaining 920M 176 is fully operational, except that it cannot read the most significant track of its paper tape input. It can nevertheless usefully read in binary paper tapes such as flight programs in ACD format, which happen not to use this track. I was hopeful that this fault’s cause would be an easily-replaced line receiver, but it is actually a fault inside the block of Araldite that holds the PTS socket onto the 920M.

EDSAC — Andrew Herbert

Several weeks in this period were very frustrating. Adding the Initial Orders function to EDSAC broke the Coincidence system that deals with addressing the main store delay lines.

Initial Orders copy the initial orders program from uniselectors to main store. Compared to normal program execution, Initial Orders run very slowly, limited by the speed at which the uniselectors can be driven. This has led to modifications to Main Control and Coincidence which have upset some critical waveform timings and levels.

This is a hard area to test because of the need to capture extended sequences of those waveforms for patient analysis by hand.

The good news is that by the 3^rd March we were seeing successful runs of basic test programs for tens of minutes.

We have run into a race condition with the paper tape reader system, leading to a modest redesign which will hopefully be implemented in the coming weeks.

Commissioning continues in the Arithmetic Unit and the Paper Tape input system. The machine has been more stable of late, although sometimes reluctant to run when first switched on.

The Cambridge University Computer Laboratory has commissioned a Blue Plaque celebrating EDSAC. The plaque will be unveiled on Tuesday 23^rd June at the Computer Laboratory in an afternoon event including a talk. See www.ccsoc.org/edsac0.htm.

Software — David Holdsworth

Consolidation

I have made modest progress in technical documentation for the server at sw-pres.computerconservationsociety.org. There is now a link to technical information which is gently growing.

Blast from the Past

Quite out of the blue, I received an e-mail from Ian Smallshire (whom I did not know) on the topic of the BBC micro Domesday project of 1986. Back around the turn of the century I worked on this as an exemplar for preservation of digital objects that were apparently inextricably bound to physical hardware. We used the BBC Domesday project as the exemplar.

Ian Smallshire has a colleague Simon Inns (IS and SI). It seems that they have copies of the original data, and (unlike the CAMiLEON project that I worked on) they have original BCPL source code. It seems that there is a worthwhile software preservation project here. I have hopes that Ian Smallshire and I can meet up soon.

In the meantime, I have been resurrecting our work of 20+ years ago. It works more impressively on younger, quicker hardware, and I am working on hosting the bulky data files on the sw-pres... server, on a blind URL. There may be copyright issues to inhibit general availability.

Atlas 1

Dik Leatherdale reports that in the expectation of more free time becoming available, he has restarted work on his Atlas 1 emulator after yet another gap of several years. When he last abandoned this work he was attempting to get the emulator to read simulated Orion magnetic tapes. Now this is more difficult than it sounds since Atlas had no means of writing Orion tapes so providing test data has to be done in a “blister” of the emulator – in essence an offline operation. Picking up where he left off several years ago the work has now been completed after several changes of format of the emulated tapes. And he found another bug in the Atlas Basic Language manual where the octal digit “8” seems to have passed unnoticed over > 65 years.

Harwell Dekatron — Delwyn Holroyd

After a long period of relatively trouble free operation the machine recently failed, the most obvious symptom being various trigger tubes lit whilst not in an arithmetic operation. I had also received a few reports that arithmetic results were occasionally ‘creative’ shall we say, so it seemed like a good opportunity to have a proper look at the machine.

The lit trigger tubes meant the anode voltage was turned on when it shouldn’t have been, which is controlled by a feedback loop in the pulse generator involving return carry B (RCB) pulses. RCB pulses should always be present when the trigger tube anode voltage is switched off (as it should be outside of an arithmetic operation) or when all trigger tubes in the arithmetic unit have fired, which indicates the arithmetic operation is complete (ignoring carry).

I discovered that RCB pulses were in fact present, but not reaching the circuit that controls anode voltage switching due to a failed ECC91 double triode valve.

Having cured the main fault, I then spent the remainder of the day checking all the other pulse generator signals. I soon discovered that the 9B-1B splitter, which should output 9 and 1 B pulses to its respective outputs from 10 input B pulses, was misbehaving. Sometimes there were 2 B pulses output from the 1B output, which wouldn’t do arithmetic accuracy any favours. Once again the fault was a tired ECC91.

Valve failures, especially the small signal types, are a very rare event on the machine. To have two failures at once is therefore extremely unusual. After a lot more checks and level adjustments no other major problems were found.

The final investigation of the day was into why one of the Dekatrons in the accumulator ended up with one less than the correct value when subtracted into, but not during addition. After a lot of head scratching the problem turned out to be the Dekatron itself. High speed filming showed that it was jumping back from 0 to 9 at the start of the operation, before stepping around correctly. But why only during subtraction?

The answer is that since subtraction requires the complement on 9, the first A pulse in the sequence of 10 is suppressed. During subtraction the first guide pulse seen by a Dekatron is a B pulse, whereas for addition the first B pulse always occurs after an A pulse. The troublesome Dekatron was jumping back from zero to 9 after receiving a B pulse without a preceding A pulse. This is a variant of the usual “sticky” Dekatron problem and the offending one has been relegated to the demonstration spinner. Over time the spinner should re-condition the Dekatron and hopefully solve the problem.

ICL 2966 — Delwyn Holroyd

On 24^th January the 2966 acquired a new neighbour. The new system is an ICL Series 39 Level 35XP, consisting of 3 storage heater sized cabinets. The node cabinet contains the OCP, 32MB store and IO couplers. The other two cabinets contain the disc controller and 5xFDS760 drives for a total of 3.8GB of storage.

By comparison, the 2966 has 2MB of store and around 7GB of storage in total, filling most of the room!

One of the unique features of Series 39 was the use of fibre optic cables to connect the processing nodes to high-speed peripherals and to each other to form more powerful multi-node systems. This 50Mbps network is known as MACROLAN. The system also supports 10Mbps OSLAN, based on Ethernet, for low speed peripherals like printers and VDUs.

The smaller systems in the Series 39 range, known as DM1, were built using custom CMOS logic arrays each containing 8000 gates. These were designed by ICL in West Gorton and manufactured by Fujitsu as part of the technology agreement between the two companies. The basic DM1 model, Level 30, was launched in 1985. Our model is from 1989 and features upgraded CMOS chips and more memory.

At the high end of the range was the Level 80, known as Estriel. Also launched in 1985, it was built using custom ECL chips which were also manufactured by Fujitsu. Compared to the 2966, Estriel was around four times more powerful with DM1 having around half the power.

Series 39 machines had the same order code as the preceding 2900 series and ran VME. Like the 2966, DM1 also had hardware support to emulate the 1900 architecture. The new system helps to round out the display and fills the gap in the timeline between the 2966 and the Trimetra.

Manchester Baby (SSEM) — Bob Geatrell

The SSEM (“Baby”) replica at SIM in Manchester has been running more reliably lately. It can still be a bit temperamental for the first 10–15 minutes after it is switched on each morning, but the problem has always settled down before any meaningful investigation can start.

As part of a recent reorganisation of the exhibits in SIM’s “Revolution” area, Baby’s surroundings have been refreshed and updated. The display boarding has been enlarged and moved further out to give the volunteers more space, including a larger backroom area, and the bright orange (Tango? ) colour scheme has been replaced by a calmer blue. The display panels now also include a SpiNNaker board from Manchester University, information about Ferranti’s early female programmers and, at last, some details about Alan Turing, including the £50 note which was first introduced to the public in this very room.

While this work was going on around it, Baby was covered with white decorator’s sheeting, which made it look like a large cartoon ghost. Thanks to Manchester University, which loaned us the full-sized 2D photo replica of Baby used for the Baby-60 event, the volunteers were still able to talk to visitors about early computing, although it lacked the impact of the working replica.

Work on the updated power supply system is taking longer than hoped. This will replace the increasingly unreliable 1990s Farnell 75V PSUs with standard commercial 48V units, adjusted to 50V, housed in a DIN rail cabinet. All the parts have now been bought, and assembly and testing will start soon.

For almost 28 years, loading patterns into Baby’s CRT store has been controlled by a program written by Chris Burton, running on a Windows XP machine. It has served us all very well, but it has had a few failures, including the cooling fan, CMOS battery and disc errors, which suggest it is unlikely to last for many more years. It cannot simply be replaced with a newer PC because it relies on suppressing interrupts in a way that is no longer supported.

I have been working on a small interface unit based on a Raspberry Pi PICO microcontroller, which will sit between Baby and a Python control program running on any nearby PC. The current breadboard-mounted prototype works well, but needs to be repackaged.

Hursley IBM Museum — Peter Coghlan

IBM System/360 model 30

The acquisition by the Museum of an IBM System/360 Model 30 has provided the impetus for our ongoing reorganisation of our rooms to help reflect a more coherent presentation of the origins of the IBM company and its ongoing evolution during the 20^th and 21^st centuries.

The Origins Room now illustrates the very early amalgamation of companies which formed the basis of electromechanical computing and data analysis, including the Dayton Scale Company, the Hollerith (Tabulating Machine) Company and Dey Time Registers (the International Time Recording Company), becoming the Computing Tabulating Recording Company in 1911 and renamed International Business Machines in 1924. Among the exhibits, the centrepiece is an IBM Coffee Grinder recently donated by Hursley’s Storage Systems Unit.

Exhibit Rooms now feature products developed exclusively by IBM Hursley; IBM Mainframe CPUs and peripherals; Mid-Range systems including AS/400, RS/6000 and System/23; a range of typewriters from the 1930s through Selectric and Golf Ball; Punch Card technology and a range of Personal Computing devices from the original Personal Computer through to final ThinkPad laptops.

Ongoing developments include a revamped Museum Website and the creation of a new Encryption Exhibit featuring the role of IBM’s Tabulating technology in decrypting wartime Enigma encrypted messages using a predecessor of the 416 Tabulator.

Readers will learn elsewhere in this edition of Resurrection that Dik Leatherdale is stepping down as editor of Resurrection to be replaced by Kevin Murrell. Please raise a glass to them both.

Additionally, Ed Smith has courageously volunteered to succeed the late Simon Lavington in charge of developing the Our Computer Heritage website. Another glass if you please!

Finally, past CCS chair David Morriss has stepped down from the Committee with our grateful thanks for his past service. Best send out for another bottle.

At the time of his sad passing, our dear friend Simon Lavington was working on a new book studying the history of British women programmers who started their careers in 1949-59. Simon’s longtime colleague, Prof. Roland Ibbett has bravely stepped in and is proposing to complete Simon’s work. Relevant material from Simon’s PC has been copied with the help of his widow Rosalind, but it is thought that some other material was held in his email account which has now been deleted by Essex University.

Roland asks whether any CCS members retain copies of relevant emails and if so whether they might be sent to . Thank you

101010101

We sometimes receive offers of documentation of long departed computers from members and others. The Society does not collect such documentation and many organisations which do are full to bursting. But for once, an offer of some early DEC Vax manuals has hit the spot with Kevin Murrell being grateful to accept them and care for them.

101010101

A member writes that he believes that the Society has an emulator for the ICL VME-based range of mainframes. He seems to have found this information in an AI-generated webpage. Sadly, like so much else which comes from AI, it isn’t true. And, even if it was, the cost of the operating system and associated software for what is still a commercial product would be prohibitive for a hobbyist.

But it is interesting to note that what Fujitsu provides to its slowly-diminishing mainframe user base are multiple Intel processors running emulation.

101010101

A researcher into the history of school computing education has asked us whether we can find issues of Computer Education, the Bulletin of the Computer Education Group of the BCS circa 1966. Amazingly Alan Pickwick has a set of this obscure publication stretching between 1969 and 2005. Job done!

101010101

We have been contacted by the author of a series of articles in Wireless World in 1967 which describe how to build a computer from some 400 reject transistors. He asks if anybody knows where the original which he last saw in the offices of Wireless World in 1972 might be.

101010101

In conversation with Dermot Turing on the occasion of his May lecture to us (well worth watching the recording if you missed it) he expressed a desire to know more about the use of punched card equipment at Bletchley Park during WW2. By co-incidence the progress report from the IBM Museum at Hursley Park (see above) suggested that it might be useful to put them in touch with one another. This has been achieved. If anything comes of it, we hope to be able to report in a future edition of Resurrection.

Then in 2008, just as I was leaving the world of employment for ever, the then CCS Chairman, David Hartley announced that the Society was looking for a new editor of Resurrection. I remembered “Jason” and thought “even I can do better than that”. After a proper job interview, there being no other candidates, I was appointed and a term of ten years was agreed.

After ten years I proffered my resignation on the grounds that one should never do a job for too long else one might become stale. The horrified looks on the faces of the committee told me all I needed to know. But now, 18 years on, it’s time for me to remove the imaginary card bearing the word “Press” from my imaginary trilby.

And what a wonderful job it has been! The chance to meet lots of interesting people with interesting things to say. I count them all as friends even though I’ve never met some of them face to face.

The Outgoing Editor

So now it’s time to say thank you. Thank you to David Hartley for giving me the job in the first place. And to “Jason” for inadvertently giving me the confidence to apply. To my friends at the BCS for their ever-helpful work (and funding) in publishing the paper copies. To Nick Enticknap for his faultless proofing. To the readers of Resurrection for giving me an incentive to put my fingers on the keyboard day after day.

But most of all to the many authors and contributors to Resurrection. Your input has made Resurrection what it is. Without you, there would be no Resurrection. Thank you for your support and friendship over 68 issues.

Please be nice to the incoming Editor, Kevin Murrell. Yes, that Kevin Murrell. Co-founder of The National Museum of Computing (TNMoC) at Bletchley Park. He needs your input every bit as much as I have.

But you haven’t got rid of me yet. I continue to manage the Society’s various websites. A complete break would be too much to bear.

Creation of the Department of Computer Science

In the late 1950s and early 1960s computing was becoming a significant requirement of much research in the natural sciences and in engineering. Universities were providing central services on an increasing scale. Among them was the University of Edinburgh, which in late 1962 advertised the post of Director of its planned Computer Unit. Sidney Michaelson was appointed in December and took up his post on the 1^st of April, 1963.

Prior to his appointment at Edinburgh, Sidney had been a lecturer in Mathematics at Imperial College London where his research on numerical analysis led him to work with colleagues on the design and construction of a computing machine. Although the only technology available to them was very elementary (Post Office relays and uniselectors), they were able to build a working system, the Imperial College Computing Engine. As part of the design they invented a technique, subsequently known as microprogramming, that has become a cornerstone of the design of almost all modern digital computers.

The responsibilities of the Edinburgh Computer Unit were to provide a computing service, to teach about computing, including what became known as Computer Science, and to do research in that subject. Joining Sidney in this venture were David Rees, Peter Schofield, Mike Osborne and Alex Wight. They were originally based in rooms loaned by the Chemistry Department but moved at the end of 1963 to No 7 Buccleuch Place. To provide a computing service, the University had committed to obtaining computer power as a remote batch service from the Atlas computer at the University of Manchester. Atlas was inaugurated on 7^th December 1962 and was, at the time, the most powerful computer in Britain. Although the University of Manchester had every good intention, the practicalities of providing a satisfactory remote service via a Post Office landline between Edinburgh and Manchester proved to be very difficult. In fact it turned out to be easier to send the punched paper tapes used for input to Atlas to Manchester via British Rail.

Edinburgh users discovered that the delay between submitting their tapes and receiving results was very variable, often stretching to more than three weeks. Naturally, this led to acrimony towards the Computer Unit, so an operator was seconded to Manchester to ensure that Edinburgh jobs received their allocated 15 minutes per day of Atlas compute time. In Manchester Sidney acquired a reputation for fiery outbursts in the face of the many difficulties which beset this venture but ultimately both sides developed a mutual and lasting respect, so much so that Sidney was one of the first external examiners for the Manchester BSc in Computer Science degree.

By the beginning of 1964 it had become clear that Edinburgh would need its own computer if Edinburgh users were to have an adequate service. A request was therefore made to the University Grants Committee (UGC) for £600,000 for a suitable machine and to the Government’s Department of Scientific and Industrial Research (DSIR) for funds to investigate time-sharing systems. The DSIR responded rapidly, saying that such an investigation was not research, so refused to fund it. However, Edinburgh was not the only university that had come to realise the scale of the costs of equipping and running a computing service and their requests led the UGC to set up, with the Research Councils, a committee chaired by Brian Flowers, at that time Langworthy Professor of Physics at the University of Manchester, to investigate ‘the provision of computers for Universities and Research Councils’. The Flowers Committee took evidence from many Universities and recommended that about £7M should be spent each year for several years to equip the universities properly. The Treasury eventually agreed to a lesser but still sizeable figure that allowed several universities to be provided with English Electric KDF9 computers. The Flowers Committee also recommended that there should be a permanent committee (instantiated as The Computer Board) to oversee the distribution and spending of that money.

For Edinburgh, the recommendations were that the academic and service activities should be separated and that Edinburgh should provide service to a (not very clearly specified) Region. So that people would still be able to run their Atlas Autocode (AA) programs on the KDF9, Harry Whitfield, Paul Bratley and David Rees wrote (in AA) an AA compiler for the KDF9, Edinburgh’s first foray into systems work. This project involved using the Atlas computer at Chilton and Glasgow University’s KDF9, since the Edinburgh KDF9 had not yet arrived. Peter Schofield and Alex Wight contributed to later versions. Flowers also took note of the interest of Edinburgh in time-sharing, so his recommendations included giving Edinburgh some responsibility for the investigation of time-sharing systems and services. This ultimately led to the creation of EMAS.

The new structure came into being on 1^st January 1966 with the creation of the Department of Computer Science and the Edinburgh Regional Computing Centre (ERCC). Sidney became Head of the Department and Dr G. E. (Tommy) Thomas, an early Manchester computing pioneer who was about to leave ICI’s management computing service, was recruited to be the Director of ERCC. ERCC was provided with an English Electric KDF9 mainframe.

Sidney was appointed Professor of Computer Science in 1967 and continued as Head of Department until 1975 when he was succeeded by Peter Schofield. Peter’s naval experiences undoubtedly influenced the way he ran the Department, steering a steady course and running not just a tight ship, but also a happy one. Non-professorial heads were unusual in those days but Peter commanded the respect not only of his professorial colleagues but also other heads of departments and the staff in the Faculty office.

By the early 1980s Peter felt it was time for him to relinquish the Headship of the Department but no candidate was forthcoming from among the professors in the Department, all of whom, apart from Sidney, held personal chairs in theoretical topics. It was therefore decided that an appointment should be made to a second established chair. Sidney encouraged Roland Ibbett, then a Reader in the Department of Computer Science at the University of Manchester, to apply. Roland had been a major contributor to the MU5 project at Manchester and he and Sidney had met regularly as fellow members of the British Computer Society’s Board of Examiners. Roland took up his appointment on 1^st July 1985 and succeeded Peter as Head of Department in 1987.

Sidney Michaelson 1966-1975		Peter Schofield 1975-1987		Roland Ibbett 1987-1995		Gordon Brebner 1995-1998
Heads of the Department of Computer Science 1966-1998 © University of Edinburgh

In 1994, Roland was appointed as a Vice-Principal of the University but continued as Head of Department until 1995, with Gordon Brebner, as Deputy Head of Department, acting on his behalf until 1995 when Gordon became the last Head of Department. In 1998 the Department ceased to exist as a separate entity and became part of the Division (later School) of Informatics, headed initially by Professor Alan Bundy. The Department of Artificial Intelligence, the Centre for Cognitive Science, the Artificial Intelligence Applications Institute, and the Human Communication Research Centre were also absorbed into the Division of Informatics.

The Edinburgh Multi-Access System (EMAS)

Although the DSIR had refused to fund the investigation of time-sharing systems, the Department of Trade and Industry (DTI) offered £250,000 to support this work, subject to matching funds being obtained from industry. English Electric (EE) agreed to provide the necessary £250,000 and Dr Thomas persuaded the DTI to provide some additional money to enhance ERCC’s service machine so that it would be able to support time-sharing. Before the project was completed however, EE was pressured by the Government into a merger with International Computers and Tabulators (ICT). The new company, International Computers Ltd (ICL), honoured the EE agreement but insisted on sending more and more people to work on the project to such an extent that it became unmanageable. As a result, after four years the University had a recently delivered machine with EE’s batch processing operating system (the Director) but not a multi-access system.

All was not lost, however. The agreement having come to an end, a new project group was put together between ERCC and the Department of Computer Science (DCS). By 1971 this group of about 9 people that included Colin Adams, Bill Laing, David Rees and Alex Wight, led by Harry Whitfield, had produced the Edinburgh Multi-Access System (EMAS) running on an ICL System 4/75. EMAS was written almost entirely in the Edinburgh IMP programming language, a development, mainly by David Rees, of Atlas Autocode. EMAS had several features that were advanced for the time, including dynamic linking, multi-level storage, an efficient scheduler, a separate user-space kernel (‘director’), a user-level shell (‘basic command interpreter’), a comprehensive archiving system and a memory-mapped file architecture.

EMAS was subsequently re-implemented to run on an ICL 2900 computer, mainly by David Rees (DCS) and Peter Stephens and Keith Yarwood (ERCC), and later by ERCC staff to run on various other systems that were used to support Edinburgh University’s central computing service. Even though slowly superseded by Unix in the late 1980s, as long as it was available, EMAS remained the preferred operating system for a significant number of Edinburgh users, including Sidney himself. The last machine running EMAS was finally switched off in 1992, the year after Sidney’s untimely death.

Computer Science Teaching

Teaching began in 1964 with the introduction of a Postgraduate Diploma in Computer Science. Undergraduate teaching began in 1965 with the setting up of the Computer Science 1 course, and the acquisition of the Department’s first dedicated computer, a DEC PDP-8 (one of the first in the UK), but it was 1968 before a follow-on course, Computer Science 2 was introduced. Computer Science 3 followed in 1970, while in 1971, the year in which the Department moved into the James Clerk Maxwell Building at the King’s Buildings campus, the first undergraduate degree, in CS & Mathematics, was created. With the creation of Computer Science 4 in 1972, the Department was able to offer a Single Honours Computer Science degree starting in 1973.

Like most degree programmes in the Science Faculty, years 1 and 2 involved students taking three full year courses, one in their chosen degree subject, one in mathematics and one other. For many years Peter Schofield taught CS1, a job few others were keen to do. He had great skill in presenting topics in a way that made them seem obvious. Peter Robertson, one of the first graduates of the Computer Science BSc, remembers the way he taught recursion without mentioning the word until the idea had appeared as something quite ordinary and unremarkable.

In the Honours years, years 3 and 4, students took term-length courses, some of which were prescribed, some of which were optional. Despite his background in mathematics, Sidney Michaelson was an engineer at heart, so the CS BSc degree included a lot of practical work, not just in terms of programming but also involving hardware. Not only did final year students undertake a significant major project, two of the third year courses were themselves major practicals, one of which was (appropriately) a micro-programming exercise using specially developed hardware. By the mid-1980s, however, not only was this hardware becoming unreliable but the Computing Officer responsible for the project left for a job in industry. At the same time, employers nationally were increasingly demanding that computer science graduates have experience of team working. At Edinburgh, Roland Ibbett persuaded his colleagues to replace the microprogramming project with a group System Design Project. Students were assigned to teams of half a dozen or so, each with a project supervisor and each being required to design and implement a system involving both hardware and software that would satisfy the set of requirements that they were all given. During the morning of the final day of the project each team gave a demonstration of their system to a small group of project supervisors and visiting industrialists. In the afternoon each group gave a “marketing” presentation to the entire class.

In 1988 a related innovation that aimed to give students “real-world" experience was the creation of Tardis. Tardis was a computing service run by students for themselves using initially a GEC63 computer that would otherwise have been destined for scrap, contained mainly in a large blue box, The idea for Tardis arose from discussion between Brian Tompsett, then a CS lecturer (and avid Dr Who fan) and John Butler, the Computer Science Service Manager. The students were told that they could make whatever use of it they liked, subject to one rule: they were not to cause any grief to the Service Manager. Tardis ran very successfully for about eight years, providing students with direct experience of managing systems. This greatly appealed to potential employers and was specially commended in a 1994 Teaching Quality Assessment report as an activity meriting promotion as an example of best practice. Eventually the services it provided became commonplace in domestic network contracts and in student halls of residence, so Tardis no longer provided a unique service and eventually succumbed to this redundancy and to the growing threat from cyber-attacks.

For their regular coursework assignments, students in the Honours years in the 1980s had access to a laboratory of 60 home-grown, networked Advanced Personal Machines (APMs), affectionately known as Fred Machines, in honour of Fred King, the Computing Officer responsible for their design and production. The origins of the APMs were in a research project that aimed to achieve three M’s (1MHz clock, 1MB memory, 1Mb/s network connection), based on the use of Motorola 68000 processors. By the end of the decade the APMs were becoming unreliable and Fred himself left, so the Department invested heavily in Sun Workstations.

External view of an APM	Internal view of an APM

Computer Science Research

In 1994 the Computer Systems Group, precursor of the present-day Institute for Computer Systems Architecture, defined itself in the first of a series of Technical Reports as being concerned with “aspects of the subject which concern the design, capabilities and performance of actual computer systems”. That report reviewed some past systems research projects in the Department and surveyed the then current interests of group members. Likewise, this paper presents some highlights of computer systems research undertaken within the Department of Computer Science but cannot claim to be comprehensive. Among other topics described in the reports are work on operating systems, sparse vector processing, human factors in computer system design, database systems and performance modelling.

Stylometry

In the early years of the Department, Sidney continued to pursue research on numerical analysis along with Mike Osborne. In the 1970s he became interested in applying computers to stylometry and worked with the University Chaplain, Andrew Morton, on a statistical study of the usage of words in literary texts, in an attempt to resolve problems of authorship and chronology. They used studies of word order within sentences to cast light on the authorship of texts ranging from the Bible and the Iliad through Elizabethan and Jacobean drama to modern criminal ‘confessions’.

VLSI

In the 1980s the development of integrated circuit technology spurred Sidney to return to his earlier interest in computer hardware. In 1981 he was Organising Chairman for a highly successful initial conference on Very Large Scale Integration, ‘VLSI 81’, held in Edinburgh. In 1982 he founded a new Working Group on VLSI for the International Federation for Information Processing; this became one of IFIP’s most active groups, regularly organising workshops and conferences. Working on VLSI with Sidney were David Rees and John Gray. Earlier, in 1980, with Irene Buchanan and Peter Robertson, John Gray had founded Lattice Logic Ltd, a company that pioneered silicon compilation. In 1989, along with Tom Kean, an Edinburgh Computer Science BSc and PhD graduate, he founded Algotronix, a company that developed a Field Programmable Gate Array based on Tom Kean’s PhD project.

In 1993 Algotronix was taken over by Xilinx, a USA-based company that was itself taken over by another American company, AMD, in 2022. Among those at Edinburgh who worked with Xilinx was Gordon Brebner, who later (in 2002) moved to California as a Xilinx employee. Gordon graduated from Edinburgh with a Computer Science BSc in 1979 and stayed on to study for a PhD, awarded in 1983 for a thesis entitled “Parallel Computation on Sparse Networks of Processors”. Gordon proved himself to be very much a computer science polymath, with interests over the years ranging from computational complexity through computer communications and parallel computing to VLSI design and programmable logic.

In the late 1990s several members of the Department contributed to the work of the Institute for System Level Integration (ISLI). ISLI was a collaborative venture between Edinburgh, Glasgow, Heriot Watt and Strathclyde Universities. It was created at the behest of Scottish Enterprise (a government agency) in response to an inward investment by Cadence Design Systems of San José, California, a leading electronic design automation software and design services company. Based in Livingston, ISLI offered a one-year MSc in System Level Integration and an EngD programme, both designed for graduates in electronic engineering, computer science and other relevant disciplines. ISLI operated very successfully until a global recession in the semiconductor industry in the early 2000s led to its closure.

Computer Graphics

Some of the graphics software used in the development of VLSI design tools in the Department derived from software created by Eric McKenzie to support the undergraduate Computer Graphics course. This course was started in the mid 1970s and was always one of the most popular CS4 courses. Some features of the course software were also adapted for use by other departments in the University running interactive graphics programs on EMAS.

Research in Computer Graphics took off when Eric McKenzie took on Martin Reddy as a PhD student. Martin’s research led to a close working relationship with vision psychologists in the Department of Psychology. They had established an Edinburgh Virtual Environment Laboratory (EDVL) that eventually transferred to Computer Science and then transformed into the Edinburgh Virtual Environment Centre (EdVEC), a joint venture between Computer Science and ERCC. EdVEC conducted both research and commercial projects in Motion Capture and Photo-realistic Rendering of real scenes for interactive experiences. Reddy’s PhD experience led him to SRI International and thence to Pixar Animation Studios where he was a CGI software lead on several Academy Award-winning movies.

Prior to any of this work in VLSI and Computer Graphics, John Oldfield had established, in 1966, a UK Science Research Council funded Computer-Aided Design Project that was later absorbed into the Computer Science Department. One of the results from this project was a program called AUTO HALAB. AUTO HALAB was designed to enable users, “without any knowledge of a programming language, to move lines, curves, and other shapes along particular paths in 3-D and fade them on and off without having to bother about the mathematical details, such as perspective”. John moved to Swansea University College in 1974, and later, in 1978, to Syracuse University where he worked mainly on VLSI design.

Computer Architecture

Roland Ibbett’s experience of teaching computer architecture had led him to believe that the workings of systems such as the Tomasulo algorithm, originally used in the IBM System/360 Model 91 computer and subsequently used in a variety of microprocessors to control the movement of operands between programmable registers and parallel arithmetic units, could best be explained by means of a dynamic visual demonstration. This idea came to fruition in the early 1990s with the design and development of HASE, a Hierarchical computer Architecture design and Simulation Environment that allows for the rapid development and exploration of computer architectures. HASE input files are used to create both a screen image of the architecture and a simulation model. When a simulation is run, HASE produces a trace file which can be used to animate the screen image so as to show data movements, parameter value updates and state changes. HASE has been used to support a number of research projects and numerous student projects and virtual laboratory practical exercises. (see ccsoc.org/hase.jpg).

Also in 1985, Nigel Topham joined the Department from Manchester where his PhD project had involved the creation of a parallel vector processing system. At Edinburgh he investigated a variety of architectural techniques aimed at increasing both the performance and energy efficiency of individual and multi-core processors. He also worked as a processor designer with several industrial concerns including ACRI, a French supercomputing startup, Siroyan and ARC International plc. At ARC he led the design of the ARC-600 embedded processor, subsequently implemented widely in many billions of chips, the second most-widely used embedded processor architecture after ARM.

Parallel Computing

Prior to Roland Ibbett’s appointment, he had given a lecture entitled “The Gigaflop Quest” in the James Clerk Maxwell Building, which the Computer Science Department shared with the Mathematics and Physics Departments and Computing Services (the successor to ERCC). This lecture had attracted the attention of several members of the Physics Department, especially Professor David Wallace. Some of his colleagues were already using various DAP computers and a few years later David’s group acquired a Meiko Computing Surface, a Transputer based system. They were struggling with the task of managing it, however, and at a meeting with Peter Williams, Deputy Director of Computing Services, Roland suggested that what was needed was a unit dedicated to parallel computing, to be organised as a joint venture between the Departments of Physics and Computer Science and Computing Services. They put this proposal for an Edinburgh Parallel Computing Centre to David Wallace and persuaded him that he should be its Director. EPCC went on to become the UK’s leading academic high-performance computing centre.

In the Computer Science Department, several academic staff had interests in parallel computing. Among them was Murray Cole who graduated in 1984 with an Edinburgh BSc in Computer Science and later with a PhD awarded for his work on algorithmic skeletons for structured management of parallel computation, with Gordon Brebner as his supervisor. After spending three years at the University of Glasgow, he returned to Edinburgh as a Lecturer in 1990 where he continued his research interests in parallel programming models, emphasising approaches which exploit skeletons to package and optimise well known patterns of computation and interaction as parallel programming abstractions.

In the early 1990s, the ALAMO project (ALgorithms, Architectures and MOdels of computation) brought together many of those in the Department who had interests in parallel computing, computer architecture and simulation: George Chochia, Paul Coe, Murray Cole, Pat Heywood, Todd Heywood, Roland Ibbett, Rob Pooley, Peter Thanisch and Nigel Topham. The project aim was to investigate the scalability and efficiency with which the Hierarchical PRAM model of parallel computation might be implemented on realistic parallel architectures.

Conclusion

During much of its existence as a distinct entity, the Department of Computer Science at the University of Edinburgh rightly enjoyed a stellar international reputation for its contributions to theoretical computer science. This tended to overshadow much of the pioneering work of colleagues whose interests lay in the area of computer systems. This article is an attempt to redress this situation, though it is inevitably an incomplete record – apologies to those whose contributions have not been included.

Acknowledgements

This article could not have been written without the work of all those involved in teaching and research in computer systems during the lifetime of the Computer Science Department. The author is especially grateful to Gordon Brebner, John Butler, Murray Cole, Eric McKenzie, David Rees and Nigel Topham for their contributions to this document and, posthumously, to Sidney Michaelson for the contents of an unpublished document written in 1988 about the origins of the Department. Thanks are also due to Chris Williams and Dik Leatherdale for their encouragement and helpful criticism and to George Ross for his preservation of historical documents.

Development Timeline

In 1947, initial development work at TRE examined the use of CRT storage as the basis of a high-speed digital computer. TREAC’s initial design and the design of a single bit, proof of concept machine were described at a conference in Cambridge in 1949. The proof of concept machine, constructed with the aim of testing circuits designed for use in the target parallel machine, was working in 1950 and used a single CRT electrostatic store of 256 bits.

The goal was to build a 20-bit machine, which would also feature a magnetic drum. The 1024 bit primary storage was to be provided by 20 CRTs each storing one bit position for 1024 address locations. The final version would have a 512-word CRT store backed by a drum, with a word and instruction length of 24 bits and the instruction referencing a single address. Input was achieved using a paper tape reader and output was by punched tape, which could be printed using a teleprinter. In addition to 2000 valves, TREAC contained 1000 germanium semiconductor diodes.

The first incarnation known as TREAC 1 ran from 1952 with further development following. Its successor TREAC 2 was used from August 1957 until March 1959 and had wired in subroutines housing commonly used subroutines stored in magnetic cores, and from August 1958 a magnetic drum. TREAC 3 ran from March 1959, had a revised set of wired-in programs and was properly equipped for drum work.

The Instruction Set and Computation

TREAC used five bits of its 24 bit word to encode the instruction and nine bits for the address it was to operate on, as shown in figure 1 below:

Figure 1 – TREAC Addressing format

There were 22 instruction codes, used by TREAC 2, covering basic arithmetic and boolean operations, conditional and unconditional branching, shift right, input and output via paper tape, magnetic drum access and access to the wired subroutine, which will be described later in the paper.

Figure 2 – TREAC schematic

The primary timing of the operation of the computer was derived from a 50 kHz basic waveform, provided initially by an electronic generator and later by a photonic wheel rigidly fastened to the magnetic drum. The latter avoided the need to synchronise a drum to the basic waveform. A schematic of the machine is shown in figure 2.

The Relation Unit (RU) was the equivalent of an Arithmetic and Logic Unit and accepted signals from the CRT store, the Accumulator, the Carry Register and Arithmetic Control to steer instruction execution. Arithmetic Control managed the information flow between the Relational and storage units during an instruction cycle or bar of four 10μs beats, giving a 40μs execution time.

When performing an arithmetic or logical operation, the contents of the accumulator and the CRT store location were simultaneously sent to the RU and when the operation was complete its output was first sent to the shift register prior to transfer to the Accumulator. To enable addition and subtraction the RU was capable of handling an additional carry bit, using the Carry Register, which took the same form as the Shift Register. In the case of a paper tape read or write instruction, the machine had to wait for the operation to complete before it could execute the next instruction.

The Control Counter (CC) held the address of the next instruction to be carried out and was incremented during beat two of the cycle. In the case of the J (Unconditional Jump) or B (Conditional Branch) instructions, which respectively affected unconditional and conditional branching, it was further modified in beat four and the next instruction was derived from the address specified the Instruction Register; unless the Accumulator was not negative for a conditional branch. In the latter case the Control Counter was not modified in beat four and control would flow to the succeeding instruction.

Figure 3 – Instruction execution

As shown in figure 3, the address selection during the action period (beats one and three) was determined alternately by the Control Counter during beat one and the Instruction Register (IR) during beat three. The Instruction Register was loaded with the instruction to be executed, which was held at the address referenced by the Control Counter. The Instruction Register held the address within CRT memory to be accessed (nine bits) and the code for the instruction to be carried out (five bits). The latter was used by Arithmetic Control to activate the different transfer gates, needed to implement the instruction, to operate in their correct order.

Since access to the CRT store was needed only in beats one and three, beats two and four were used for regenerating the information held there. Access to the store could be limited to regeneration during beat four, because the single address architecture used required transfer of the operational result from the Shift Register to the Accumulator Register. Moves out of the Shift Register were controlled by the Transfer Unit. The T instruction could be used to transfer the contents of the Accumulator Register into store, on the third instruction beat of its execution. Access to the CRT store was prevented during regeneration periods. The Regeneration Register sequentially tracked the addresses being regenerated during the regeneration beats, allowing the process to execute without interruption. Output from this register provided the CRT store deflection amplifiers with the requisite signals in digital form.

CRT Storage

An electron beam, with enough energy, hitting a phosphor dot on a CRT screen resulted in electrons being emitted, which were attracted back to the screen surface close to their origin. The resulting positively charged well represented a “1” bit (the absence of charge was taken as “0”) and was short lived as it attracted the emitted electrons back to it. Information could be available for a few milliseconds or up to a quarter of a second after the beam had moved on, and hence needed to be regularly refreshed. A bit could be erased by stimulating an adjacent area, often as a short dash, creating a second well, surrounded by a halo of electrons, which leaked into and eliminated the first (dot) area of charge, making it a zero.

Information was read from a thin metal sheet, known as a pick-off plate, placed in front the CRT screen, which detected changes in the electrical characteristics of the phosphor through a micro-capacitive effect. A read involved first sending a pulse to the bit to be read; if this was already a “1”, then no change in charge was seen at the plate, but if it was zero a change was detected. The bit that was read had to be immediately re-written. The entire display had to be periodically refreshed using the same basic method.

This “Dot-Dash” technique is not sufficiently robust for use in a parallel computer and data could be lost. The Manchester team identified an alternative method known as focus-defocus, which the TREAC team adapted for use in the parallel computer. In the focus-defocus method a highly focussed electron beam was used to generate a “1” signal and as before this could be read using a further pulse; if the spot being read had held a charge, then the change in electrical status would be detected by the pickup plate. A defocussed beam, which generated a more diffuse spot with lower charge density, concentric about the original beam position could be used to erase a bit. This approach was less sensitive to errors in the deflection system and gave increased bit density and better regeneration characteristics than the “Dot-Dash” approach.

TREAC used 24 CRTs, each capable of holding 512 bits, corresponding to each of the 24 bits of the word, arranged in order of significance.

Magnetic Core Storage

From January 1958, the existing CRT store was supplemented with a small array of magnetic cores, which would be used to house some commonly utilised subroutines, known as the wired subroutines. This memory comprising 480 2mm, ferrite ring cores, was known as the wired store and came into use in late 1957 under TREAC 2. This was expected to almost double the effective speed of the computer and to support around 29 subroutines; additional subroutines could be loaded into main store from short lengths of paper tape.

Wired subroutines were not held in CRT memory and could not be accessed using a simple jump instruction; instead the ‘flash’ order Q, whose operand field indicated the target subroutine, was used. The wired subroutine used the low address areas of main store for transferring information to or from the main routine, typically using locations 0, 1, and 4 to 12, with parameters passed in locations 0 and 1.

The core was arranged as 32 vertical columns of 15 2mm cores, accommodating 32 15 bit instructions; 5 bits recorded the Operation Code, 9 detailed the address, and an additional bit specified if the next instruction was to be obtained from CRT memory or from core store. As shown in simplified form in figure 4, the cores were threaded with the following control wires:

The Master Wire threaded through all 480 cores and was used to clear the cores, placing them in a zero state.

A set of 64 setting wires was used to encode the subroutines, generally using one setting wire per subroutine. A subroutine of longer than 32 instructions might require the use of two or more setting wires, while for shorter subroutines, two could be stored on one wire. A “1” was encoded when the setting wire passed through a core and “0” when the setting wire bypassed the core, a setting wire thus traversed some, but not all of the cores of the matrix.

Figure 4 – Simplified schematic for TREAC magnetic cores.

32 read wires, each one threading through the set of 15 cores that made up a single instruction, these provided the means for selecting the instruction to be read.

15 output wires each one corresponding to the one of the 15 digits of an instruction.

The process for loading and reading a subroutine began by pulsing the Master Wire to set all cores to zero. A pulse was then sent down the Setting Wire to place cores that the wire passes through into the “1” state, leaving the cores it does not pass through in the zero state. The required instruction could be read using a pulse on the appropriate reading wire, which resulted in the output lines delivering a negative pulse whose amplitude was governed by whether a “0” or “1” was held in the core.

The Setting and Master wires were provided using a fine wire to allow a large number of wires to pass through each core. The read and output wires were thicker, forming a stronger framework for the cores to rest on. There were sets of 64 small tags (arranged in an 8 × 8 matrix); with 17 sets above and 16 below the cores. Each instruction in the selected sub programme ran from the appropriate tag at the top to the corresponding tag at the bottom and then back up to the next column and so on, via the Setting wire.

Once the subroutine was selected through activation of the appropriate setting wire, an independent 4 × 8 matrix of ferrite cores was used to address the particular instruction to be read. The 32 output windings of this matrix were connected to the 32 Read wires attached to the 2mm core memory, and the one activated caused the value held by each core in that row to be put out on the 15 output wires. The design had many similarities with the EDSAC II reserved store approach.

The Magnetic Drum

Whilst work on the magnetic drum began in 1947, it was not until August 1958 that a working instance was installed and working on TREAC. Yet the Birkbeck and Manchester machines had drum storage by 1953 and ACE and DEUCE had such devices by 1955.

A prototype drum was available, albeit without a machine to test it on, in 1949. Further investigations refined the best design, approach to data transfer, and mechanisms for read/write head movement. The parallel nature of TREAC made implementation more complex than the serial designs deployed elsewhere. Management of machine cycles to allow interleaving of drum activity with the CRT refresh process was an additional challenge.

The designs tested were based on a magnetic oxide coated drum, four inches in diameter, but varying in length between one and ten inches and with a target capacity varying between 2028 and 64000 words. One design offered capacities of 8192 or 64000 words; to achieve the latter required the bridge carrying the heads to be oscillated, increasing the mean access time from 20 to 1250 milliseconds. Subsequent designs were more conventional, however by late 1956 lack of a drum was seen to be delaying progress in developing automatic programming techniques.

The final design was a four inch diameter drum, nine inches long, holding 8192 addressable words. The track access was through a moveable carriage holding the 26 recording heads; 24 were used for recording, two were spares. There was a gap of 31 track widths between the heads and the carriage could take up to 32 distinct positions, however the accuracy of the head positioning mechanism meant only eight could be used. Data transfers between main memory and the drum, which held 8l92 words of data, worked in parallel mode and utilised 8 available groups of 24 tracks, individually selected by a moveable head assembly. Each group of tracks held 32 blocks of 32 words. Machine orders C, n (Calling) and either K, n (Keep) in the case of TREAC 3 or L, n (Load) for TREAC 2, transferred the information to or from the next 32 words in memory, from or to block n on the drum. Control then flowed to the order below the 32 word block used for the transfer, as shown in figure 5.

Figure 5 – Instruction format and physical layout for a drum operation

The location being accessed was derived from a photonic wheel (a change from the original phonic wheel design) of 1024 equally spaced radial lines, the starting point being specified by a single toothed wheel, which was monitored by a magnetic pickup head. A series of binary counters (0,1023) tracked the photonic wheel and incremented as each mark passed between a light source and a photocell. The transfer address was held in a binary register and the machine waited until the monitoring counter was the same as the transfer address before the transfer began. Synchronising of the transfer between the main storage and drum was achieved through deriving the machine timing cycle directly from the drum; in its final form the drum rotated at 2400 rpm, resulting in a beat time of 15μs. Head movement was initially engineered using a complex pneumatically operated system, which was later replaced by a relatively simple, but sufficiently accurate system of lever linked solenoids.

Initial Load Mechanism

The TREAC initial input routine was loaded into the electronic store using a motor driven uniselector, which had 51 positions and 16 banks of contacts (figure 6) and capable of transferring 16 digits. In practice 12 banks were used, five for the bits signifying the operation code and seven for the bits encoding the address, giving an address range of 0 to 127. Figure 6 – Example of a 16 level bank uniselector (see ccsoc.org/treac0.htm) The motor in the uniselector moved the wiper on one position round the bank for each word in the initial load program, each bit being read from successive levels (layers) of the uniselector, with the exception of bits 8-19, which were all set to zero. The pattern of binary digits required was obtained by connecting the corresponding uniselector contacts to a voltage source, if a “1” is desired or connecting them to earth to give a “0”. It seems to follow the principles set by EDSAC but with significant technical differences due to: the different memory technologies used by these machines, TREAC not having a hardware multiplier and different uniselectors being used. Figure 7 – Simplified schematic of initial load mechanism This routine could then be used to load a program tape containing the user program and associated library routines. Instructions on the tape were punched in the order: decimal address digits, code letter, operation code; this was known as standard tape encoding. Instructions were read in, and depending on control sequences included on the tape and on the code letter, could be loaded into a particular location in memory. This provided the potential for relative as well as absolute addressing, making the programmer’s life easier. The instruction in the initial input routine which transferred a completely assembled instruction to store was called the transfer instruction. The simplified process is shown in figure 8. Figure 8 – Simplified Initial Load Process This method of loading programs was superseded with the advent of TREAC 2 in 1957, when it was replaced by a mechanism which utilised a wired subroutine, held in the magnetic core store. Programming The original machine used a tape code known as “1953 standard code”, which was converted into machine code by the initial input routine. A modified form of this, known as Mark 4, added new operations and floating point arithmetic, which whilst using identical operational codes to integer arithmetic was more complex and utilised a large wired-in subroutine known as an ‘interpreter’, which allowed the machine to act like a floating point computer. One consequence of this was that floating point arithmetic placed a heavy load on the machine, slowing it down by a factor of 10. Floating point numbers were expressed as separate fractional and exponent parts. This code type enhanced the options available for absolute and relative addressing available under standard code and was enabled using a compiler, which allowed the conversion of the new code format into machine code. This process included address resolution and provided access to a richer subroutine library. In early 1959, Mark 4 tape code was superseded by Mark 6, which was valid only for TREAC 3 and came in with the magnetic drum. Mark 6 was structured to read like standard code and was converted into machine code using a compiler or translator. It also provided an indexing capability and floating point arithmetic. Depending on how the machine was started TREAC 3 could accept either standard or Mark 6 code. A high level algebraic input code, designated Mark 5, was available in 1959; long term only the standard, Mark 5 and Mark 6 codes were expected to survive. Sophisticated debug facilities were available under both Mark 5 and Mark 6. Mark 5 was a rudimentary “high-level” programming language that aligned with mathematical notation. It could handle both integers and floating point numbers. Variables could be grouped and indexed in the equivalent of an array. Auxiliary variables could be housed on the drum. Code statements were held in blocks that were subdivided into clauses; a branch to another clause could be effected using a DO statement, which was effectively a “go to” type of instruction. There was an IF statement that worked with DO to give conditional branching. The operators for logical and algebraic manipulation were identical, operation switches between them using LOGIC and ALGEBRA commands. Nested subroutines were supported. The Mark 5 translator could be read in from tape or held on the drum. Programs were punched on a perforating teleprinter adapted to Mark 5 symbolism and the resultant tape was fed into the reader. An intermediate tape was punched as a result; this acted as the input from which the final program tape was produced, comprising three parts, only one of which, the code section expressed as standard code, could be run. Under TREAC 3, a large program could consist of subprograms able to be divided into instalments each of which could be held on the drum. The instalments could be loaded in store and control transferred between them, using special routines, driven by three parameters, the length in words of the instalment, the starting block on the drum of the instalment read in and the location where the code is to be loaded. Conclusions The parallel nature of memory access used was novel; previously all other cathode ray storage based machines accessed memory in a serial fashion. The machine was an early adopter of magnetic core as a fast supplementary store in 1957. TREAC was developed in an evolutionary manner and whilst the use of a magnetic drum was envisioned from an early stage, it was not successfully implemented until 1958. The instruction set and the initial load mechanism resembled that of EDSAC, the latter being published in 1950, although there are some differences between the two. In scientific use, it would be imagined that lack of a hardware multiplier would be a handicap. By the early 1960s TREAC’s hardware was becoming unreliable and it was switched off in 1962 to be replaced by RREAC (RRE Automatic Computer) a transistor based machine again designed in-house.

Obituary: Sir Tony Hoare FBCS (1934–2026) Jonathan P. Bowen Tony Hoare during the 2018 celebration at the BCS London office for the 20th anniversary of his book, Unifying Theories of Programming. (Photograph by Jonathan Bowen.) Professor Sir Charles Antony Richard Hoare, the pioneering computer scientist who taught us that programming is as much a branch of logic as it is a craft, has left a legacy as enduring as the algorithms he devised. Known to most as Tony Hoare, he was the creator of Quicksort, the recursive work of genius that has remained the benchmark for sorting efficiency for decades after its 1959 inception. Born in Colombo and classically educated at Oxford University, Hoare’s career path was unusual for such a background 1 . His time in the Royal Navy and his studies in Russian statistics paved the way for a career defined by rigorous clarity. Beyond the speed of Quicksort, his true passion lay in correctness. With the development of Hoare Logic and Communicating Sequential Processes (CSP), he provided the mathematical underpinning necessary to reason about imperative programs and concurrent systems. He sought to turn the “art” of programming into a disciplined science. Ever humble and possessing a sharp wit, Hoare was willing to be candid about his “billion-dollar mistake” – the invention of the null reference. He spoke of it not with defensiveness, but with the wisdom of a man who understood that even geniuses can stumble regarding complexity. His 1980 ACM Turing Award was not just a recognition of his technical brilliance, but of his role as an ethical philosopher for the computing world. Tony Hoare’s influence resides in every line of verified code and every high-level language that prioritises safety over shortcuts. He leaves behind a digital world that is potentially more orderly, provable, and elegant because he chose to look beyond the syntax, to consider the semantics of systems. He was a logical conclusion of a well-lived life. 1. Sir Tony’s description of his early career can be found in Resurrection 48. [ed]

Obituary: Frank Land OBE, FBCS (1928-2026) John Aeberhard * Frank Land who died in May at the age of 97, was successively a pioneer of the LEO computer, the first British academic in the field of systems analysis, and after retirement a leading light in the LEO Society. Frank arrived in England as a ten-year-old refugee in April 1939, the son of a German Jewish family fleeing persecution. After elementary school, he attended Willesden County Grammar School. He then secured a place at the London School of Economics, graduating in 1950 with a degree in economics. In 1952, Frank joined the J. Lyons Company as a clerk in its statistics office. At that time the company was developing Lyons Electronic Office, Britain’s first business computer. After passing an aptitude test he was selected to work on the project. When Lyons spun off Leo Computers Limited in 1954, Frank took on leading roles in the new company, and in the successor companies after it was acquired by English Electric in the early consolidation of the UK computer industry. In 1967, Frank changed career direction to take up a newly established post in what later became the Department of Information Systems at the LSE. There he was an advocate for a socio-technical approach to business information systems. He became professor of information systems in 1982. In 1986, he became professor of information management at the London Business School, retiring in 1991. In retirement, Frank worked tirelessly for the LEO Computer Society, co-authoring User Driven Innovation: The World’s First Business Computer (1996). He was appointed OBE in the 2019 Birthday Honours for services to the information systems industry. *Precis by Martin Campbell-Kelly.

Aims and Objectives The Computer Conservation Society (CCS) is a co-operative venture between BCS, The Chartered Institute for IT; the Science Museum of London; The National Museum of Computing (TNMoC); and the Science and Industry Museum (SIM) in Manchester. The CCS was constituted in September 1989 as a Specialist Group of the British Computer Society. It is thus covered by the Royal Charter and charitable status of BCS. The aims of the CCS are: To promote the conservation of historic computers and to identify existing computers which may need to be archived in the future, To develop awareness of the importance of historic computers, To develop expertise in the conservation and restoration of historic computers, To represent the interests of Computer Conservation Society members with other bodies, To promote the study of historic computers, their use and the history of the computer industry, To publish information of relevance to these objectives for the information of Computer Conservation Society members and the wider public. Membership is open to anyone interested in computer conservation and the history of computing. The CCS is funded and supported by voluntary subscriptions from members, a grant from BCS and by the free use of the facilities of our founders. Some charges may be made for publications and attendance at seminars and conferences. There are a number of active projects on specific computer restorations and early computer technologies and software. Younger people are especially encouraged to take part in order to achieve skills transfer.